Feedback circuit eliminates CCD-driver delay mismatch
Edited by Bill Travis
Mike Wong, Intersil-Elantec, Milpitas, CA -- EDN, September 18, 2003
In a CCD (charge-coupled device), packets of charges shift across the array. The transistor array, also called a bucket-brigade shift register, receives drive from a dual-phase clock signal. Dual-phase clock signals comprise two synchronized clock signals that are 180° out of phase. High peak-output-current CCD drivers can buffer the logic-level clock signals and turn them into high-voltage and high-peak-current signals to drive the heavily capacitive gates of the many CCD transistors. Because of the speed mismatch of CCD-drivers' n- and p-channel FETs, the turn-on and -off delay times are poorly matched. Figure 1 shows the outputs of one such current CCD driver, Intersil's EL7212 (www.elantec.com), with a dual-phase input clock. The overlap in the output stems from the turn-on and -off delay mismatches of the EL7212.
In a low-resolution system with a lower clock frequency, the delay mismatch is an insignificant part of the clock period. As CCD scan rate increases, the mismatch becomes a large part of the clock period. You need a new approach to correct the CCD-driver delay mismatch. Figure 2 shows a circuit that uses amplifiers to sense the delay mismatch and correct it. Because 
and VOUT are 180° out of phase, if their turn-on and -off times coincide perfectly, the voltage between R4, R7, and C2 is 1/2VCC. Amplifiers IC2A and IC2B compare voltage on C2 with the 1/2VCC reference voltage and adjust the voltage between R3 and R6. IC2A provides the phase inversion, and IC2B is the high-dc-gain error-correction amplifier. The output of the error amplifier drives R3 and R6, which shift the voltage offset of the incoming clock signal. When the offset-voltage level of the input clock signal shifts, the time at which the CCD driver is triggered also shifts. IC2A and IC2B guarantee that the proper offset voltage goes to the input clock signals so that the delay mismatch cancels. D1 and D2 rectify the input clock signals and create the supply voltage to the IC2A and IC2B amplifiers. When the input signals are removed, the power to the amplifiers shuts off, and the error-correction loop deactivates to prevent output oscillation with no inputs.
