Verification platform adapts to your needs
By Gabe Moretti -- EDN, April 17, 2003
The Incisive verification platform from Cadence includes three simulation-environment family members. The core product, a single-kernel, multilanguage simulator, accepts designs in Verilog, VHDL, SystemC, and Cadence's SPW and AMS languages. The AMS language environment combines both proprietary and standard languages to support mixed-signal designs. Engineers can use AMS with Spectre; the company's version of Verilog-AMS; Spice; and standard languages, such as VHDL-AMS, VHDL, and Accellera (www.accellera.com) Verilog-A. The base product supports the unified simulator with Verilog, VHDL, and SystemC and offers transaction-level simulation and unified test generation. It also provides one user interface, regardless of the input language you employ.
The Incisive-XLD product allows design teams either to acquire as many as 10 licenses of Incisive or to use a local or a remote Palladium accelerator/emulator box, depending on requirements. This feature allows design and verification teams to work interactively during the day and run as many as 1 billion verification cycles at night. Incisive-XLD Base, the most powerful member of the product family, includes a dedicated Palladium accelerator/emulator with the base product.
Although the single-kernel architecture supports both SPW and AMS environments, you must purchase these modules separately. The Incisive verification platform is available on HP-UX, Solaris, IBM AIX, and Linux operating systems. Prices start at $27,000 for Cadence Incisive, $200,000 for Incisive-XLD, and $360,000 for Incisive-XLD Base.
Cadence Design Systems, 1-408-943-1234, www.cadence.com.
