FPGA adopts a revolutionary stance
By Brian Dipert -- EDN, April 1, 2004
Darwin figured out that measured evolutionary steps, not abrupt revolutionary leaps, are the preferred way of the world. In your engineering-problem-solving approaches, many of you have figured it out, too. Sometimes, though, the rules of the game change, and continued evolutionary investment leads to diminishing returns; those situations require a revolutionary alternative. Xilinx (www.xilinx.com), for example, doubled the number of four-input LUTs (look-up tables) and registers in each configurable-logic cell, or “slice,” when moving from XC4000 to Virtex FPGAs and again from Virtex to Virtex-II.
Altera has historically made comparatively minor enhancements to its own LAB (logic-array block), containing eight to 10 LE (logic-element) pairings of a four-input LUT and register, beginning with its first-generation 1992 Flex 8000 family and extending all the way through 2002’s Stratix devices (see “Congratulations to EDN’s Innovation 2002 winners,” EDN, May 1, 2003, pg 22). Now, however, the company has taken the revolutionary plunge and created an ALM (adaptive-logic module) for the Stratix II family (Picture). Altera’s past logic-block conservatism had merits; fundamentally, it gave front-end synthesis and back-end placement-and-routing software a consistent, predictable silicon platform on which to perform and perfect its compilation magic.
Using a coarser grained logic element, however, also has advantages, especially in the modern era of perpetually leaky smaller-than-100-nm transistors. Increasing the amount of fast, silicon-efficient intralogic-block routing potentially reduces the necessity for comparatively costly and slow interblock-routing resources, along with the power-consuming configuration bits for that routing. The larger the fundamental logic block, though, the greater the importance that your design software make optimal use of that logic block’s attributes—both its internal resources and its available inputs and outputs. Otherwise, expensive silicon goes to waste.
Peer inside a Stratix II ALM and you’ll find a collection of logic functions: two four-input LUTs, a three-input LUT, two registers and two three-input adders, for example. In striving to assist design software in making efficient use of the ALM, Altera has built it in such a way that its triple-LUT structure can implement a diversity of functions. Also, with efficiency aspirations in mind, Altera has doubled the number of inputs to and outputs from each ALM compared with the LE predecessor. Eight ALMs combine to form each LAB. Curiously, competitor Xilinx dropped the three-input LUT from its logic block as part of the several-year-old XC4000-to-Virtex transition, citing synthesis tools’ dearth of use for them. Altera claims that it resolved this issue, however, in part because the HDL-friendly three-input LUT in Stratix II’s approach resides ahead of the four-input LUTs, not after them as in the past Xilinx implementation.
You won’t unfortunately be able to test Altera’s hypothesis on real chips until next quarter when the first Stratix II customer samples are scheduled to begin rolling off partner TSMC’s (www.tsmc.com) production lines based on a 90-nm, low-K, copper process. Altera’s latest generation Version 4 Quartus II design software offers preliminary device support, however, so you can now begin your development. Due to appear first, the EP2S60 ($125, 25,000, end of 2004) contains 24,176 ALMs, 2.5 Mbits of SRAM, 144 18×18-bit multipliers, and 12 PLLs. The family of six Stratix II devices, when all members are available for sampling by year-end (with subsequent production, along with HardCopy variants, scheduled for the first half of 2005) will range from 6240 to 71,760 ALMs and contain as much as 9.3 Mbits of SRAM. All Stratix II chips also support nonvolatile 128-bit AES security for their links to external configuration memories, along with 1-Gbps differential source-synchronous signaling and dynamic phase alignment.
Altera, 1-408-544-7000, www.altera.com.
