Can you C acceleration?
By Robert Cravotta -- EDN, June 10, 2004
The Stretch S5000 family of software-configurable processors allows you to create hardware-acceleration blocks and extend the processor-instruction set of an Xtensa-based RISC-processor core based on your application’s C/C++ code. User-defined instruction extensions reside within the ISEF (instruction-set-extension fabric), which is a proprietary programmable-logic block that interlocks with and interfaces with the RISC-processor pipeline (Picture). The Stretch C compiler implements the hardware-acceleration blocks by analyzing the C/C++ code that you manually mark after profiling your code and identifying the performance hot spots. Stretch intends the C compiler to be the only tool for implementing the hardware-acceleration blocks, so you may have to manually restructure your target C/C++ code, based on a set of guidelines from Stretch to assist the compiler to squeeze the most performance from a block of marked code. Instrumenting your software source code so that the compiler can optimize how it implements the hardware-acceleration blocks does not break the portability of your code.
Stretch has not disclosed the organization details of the ISEF, which accesses data through a 32×128-bit register file using three 128-bit input paths and two 128-bit output paths. The wide register file tightly couples with the Xtensa registers and memory. The Stretch C compiler creates and schedules the user-defined instructions in the ISEF so that they are fully pipelined and interlocked with the Xtensa core so that instructions that cannot complete in one cycle are spread over the necessary number of cycles.
The S5610 is the first of three devices in the S5000 processor family that will be available this July for $100 (10,000). The S5500 and S5400 are lower cost devices that will become available in the months following the availability of the S5610, and they will offer the same S5 processor engine and memory resources, but they include fewer integrated I/O peripherals, interfaces, and smaller packaging. The S5610 operates at 250 or 300 MHz and includes 256 kbytes of on-chip SRAM, an MMU, 64-bit DDR-400 SDRAM with ECC, PCI-X, 64-bit SysAD, and four 10/100/1000 Ethernet MACs (media-access controllers).
Stretch,1-650-864-2700, www.stretchinc.com.
