The best of both (logic) worlds?
By Brian Dipert -- EDN, April 15, 2004
Structured ASICs and high-density FPGAs both attempt to address chip designers’ demands for devices with traditional ASIC-like high speed, high density, low per-gate cost, and low power consumption but without ASICs’ increasingly high NRE (nonrecurring engineering) charges and lengthy delays from design completion to the arrival of first chips in hand (see “Silicon segmentation,” EDN, Sept 18, 2003, pg 57). Neither silicon extreme is ideal for all possible applications, though, and Leopard Logic thinks there’s plenty of room left over for its in-between, mutually encompassing CLD (configurable-logic device) approach.
In its initial incarnation, Leopard Logic was a provider of embedded FPGA IP (intellectual-property) building blocks to ASIC and foundry suppliers. However, the company obtained insufficient industry interest—a situation, the company claims, resulting from the sluggish financial-investment market of recent years, not reflecting any fundamental invalidity of the company’s technology. So, Leopard Logic decided to reinvent itself as a silicon supplier, thereby competing with its former potential customers.
Leopard Logic’s Gladiator devices combine HyperBlox MP (mask-programmable) and FP (field-programmable) logic modules, DLLs and PLLs, dual-port SRAM arrays, and MAC (multiply-accumulate) circuits on a single chip, encircled by a configurable-I/O ring (Picture). FP and MP logic blocks are functionally identical, simplifying EDA tools’ efforts, but, whereas SRAM elements configure the FPs when the chips are in customers’ hands, a single via layer customizes the approximately 20-times smaller MP blocks during the final stages of device fabrication. Robust, hierarchical interconnect structures tie the FP and MP subsystems together and to the remaining circuits on the device.
Leopard Logic is focusing its initial ToolBlox script and library support on Synopsys’ ubiquitous Design Compiler, and it also anticipates offering Mentor Graphics support. The company plans to offer a range of devices with varying achievable gate counts and amounts of various on-chip resources (Table 1). The initial CLD6400 device, fabricated on TSMC’s 0.13-micron process, is now available and is forecast to cost $95 (100,000) in early 2005. Leopard Logic estimates that it can turn around product samples in less than four weeks after you ship the company $50,000 in NRE charges and a compiled bit stream representing your design.
Leopard Logic, 1-408-777-0905, www.leopardlogic.com.
