Simple emulator speeds testing
Edited by Bill Travis
Navdhish Gupta, Chicago, IL -- EDN, September 25, 2003
Designing and testing embedded hardware can be frustrating if you have to rely on somebody else's perhaps-unready firmware to test your hardware. Often, hardware is ready for testing before debugging and system firm-ware are available from software developers. Microprocessor emulators are solutions but are often expensive, hard to use, and sometimes inappropriate for use by hardware developers, who often just need to read and configure registers on devices on their boards. If you are not primarily concerned with your processor's bus performance and need simple read and write access to registers on chips on your board to configure and test hardware, then building a simple processor-bus emulator, such as the one in Figure 1, may be an attractive option. The simple emulator shown uses an easy-to-use Basic Stamp microcontroller (www.parallax.com) on a carrier board and a small CPLD to emulate a 16-bit "ISA-like" I/O bus. Figure 2 shows the timing parameters for the bus (Figure 2a shows write-cycle timing; Figure 2b shows read-cycle timing). Note that the bus emulator runs much slower than a "normal" processor bus but is useful to read and configure registers that you need to test hardware. This design uses the 16-bit ISA-like bus mainly for illustrative purposes; you could emulate almost any processor bus with a similar setup.
The simple emulator consists of two parts, the hardware (Figure 1) and the Basic Stamp firmware (Listing 1). You must connect the emulator itself to a 5V power supply and a PC with a keyboard, monitor, and serial port, and you load any simple terminal-emulator software, such as Hyper Term. The serial programming cable you use to program the Basic Stamp also communicates with the terminal-emulator software by inserting a switch, S1, that lets you disconnect or connect the DTR/ATN connection. When the switch is closed, you can program the Basic Stamp, and, when it is open, you can use the terminal-emulator software to communicate with the Basic Stamp. You enter commands on the keyboard, and the results appear on the monitor. The emulator connects to the board and devices to test and configure, such as a custom FPGA, through the board's normal processor bus. (You need to either socket the original processor or provide a test port on the board.) You tristate the original processor or remove it from the board to use the emulator.
The Basic Stamp firmware emulates processor-bus cycles by changing the appropriate control signals on its pins. The CPLD uses shift registers to interface the serial address and data into and out of the Basic Stamp to the emulated 16-bit parallel address- and data-bus signals. The CPLD also "conditions" the control signals from the Basic Stamp to the emulator header by performing logic-threshold conversion through CPLD I/O buffers. Listing 2 shows the Verilog code for the CPLD. Note that, although the control signals IOW, IOR, BALE, and ENDIR come from the basic code firmware and the Basic Stamp pins and are conditioned through the CPLD; they could come directly from a simple finite-state machine in the CPLD if your design requires more realistic bus timing. The Lattice (www.latticesemi.com) ispMACH 4128V CPLD is a 5V-tolerant device whose inputs you can safely drive with voltages as high as 5.5V. It also supports as many as 64 I/O lines and is in-system-programmable through the IEEE-standard 1532 interface. These features make the CPLD a good choice for use in the hardware implementation of the logic needed in the emulator.
