Processors provide Layer 2 traffic management
By Nicholas Cravotta -- EDN, January 22, 2004
Mindspeed Technologies has announced the TSP3 family of programmable traffic-management processors, enabling product differentiation at Layer 2 through traffic-management capabilities, including queuing, hierarchical shaping, scheduling, policing, congestion management, customization statistics, and switching of as many as 256,000 packet or cell streams (Picture). The family also supports transport of Layer 2 frames over MPLS, IP-to-ATM (ATM Adaptation Layers 2 and 5 segmentation and reassembly), Ethernet-to-ATM, frame relay-to-ATM, and IMA (inverse multiplexing over ATM).
The OC-48 M27483 architecture employs two programmable 32-bit RISC Octave microprocessor cores with multiple coprocessing engines and specialized traffic-management instructions, such as classification, context prefetching, data transformation, and multilevel shaping, to achieve wire-speed processing.
Companion PortMakerIII firmware allows the addition of new features to deployed devices through downloadable software upgrades and includes Ethernet-enabled packet- and cell-traffic management and Ethernet-to-ATM bridging. The initial binary-application package in-cludes ATM Adaptation Layer 5 with ATM-to-MPLS (multiprotocol label switching), enabling efficient use of bandwidth when transporting legacy ATM cell traffic over MPLS networks. Datapath interfaces include Ethernet, POS (Packet over SONET), Utopia, and PCI. A source-code license is available.
By offering a range of port speeds and application firmware, developers can create a single hardware design supporting multiple port speeds across a range of enterprise; access; and metropolitan-network applications, such as DSLAMs (digital-subscriber-line-access multi-plexers), digital loop carriers, cable head ends, and fixed and mobile wireless gateways.
The 622-Mbps, OC-12 M27482 costs $250 (1000), and the 2.5-GHz, OC-48 M27483 costs $425 (1000). Both devices will become available for sampling in November. Lower speed members of the family, the 15-Mbps, OC-3 M27480 and 310-Mbps 2xOC-3 M27481, are both slated to become available for sampling in the fourth quarter of 2004. The TSP3 (board-development kit) includes a reference design for system simulation, including chip model, testbench, and diagnostic code for hardware-design verification.
Mindspeed Technologies Inc, www.mindspeed.com.
