FROM EDN EUROPE: FPGA tools follow ASICs into physical awareness
By Graham Prophet -- EDN, January 8, 2004
If you are designing with the latest generation of complex FPGAs, you will find yourself subject to the same problems that have beset complex ASICs for some time—issues such as modelling gate and interconnect delays to achieve timing closure. In the same way that ASIC design had to move to an integrated design-tool flow from high-level design to layout to resolve these problems, FPGA tools must now migrate in the same direction.
Mentor Graphics' offering for this sector is its Precision tool set. Precision Synthesis augments RTL (register-transfer-level) synthesis with "physically aware" data representations that follow the FPGA vendors' design rules to carry out placement modification, retiming, replication, and resynthesis operations. You can control these operations through an interactive user interface called Precise View, which allows multiple-domain insights on the coding changes' effect on physical placement and resulting performance. The process of recoding problem sections of logic and hoping that timing improves is now unrealistic and can lead to long delays in achieving desired performance, Mentor asserts. As with ASIC technologies, interconnect delay can now account for 70% of overall delay, and physical layout is critical. Using PreciseTime's incremental timing analysis to understand the sources of performance issues, you can cross probe between RTL, schematic, physical, and timing views to identify bottlenecks. Pricing for the tool set begins at $35,000.
Mentor Graphics, +44 1635 811411, www.mentor.com.
