FROM EDN EUROPE: The home-study route to DSP
Many embedded-system engineers regard digital-signal processing as a math-heavy black art that they'd rather avoid. But when an application finally surfaces that defeats traditional approaches, it's time to take up the mantle. It may be far easier than you thought.
By David Marsh, Contributing Technical Editor -- EDN, September 4, 2003
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The first commercially available IC digital-signal processor—Intel's 2920—was replacing analogue filter banks in full-duplex, 1200-bps, digital hardware modems as early as 1979. At the same time, rapidly growing numbers of microprocessors and peripherals increased the feasibility of handling signals in numerical representation. Until about that time, just about any commercial signal-processing task required analogue computation, with complex feedback loops and compensation circuits to maintain stability. Alternative techniques that relied on bit-slice-processor minicomputers and data-acquisition hardware were seriously expensive, and often appropriate only for researchers. The appealing logic of being able to economically digitise signals and perform math in the digital domain, alleviating drift and other inaccuracy terms that were also expensive to tackle with analogue techniques, led directly to the multiple families of DSPs available today.
With some form of DSP now lying at the heart of products ranging from answerphones to washing machines, it's easy to forget just how recently this revolution came about. And, until recently, the sharp division between a general-purpose microcontroller and a DSP chip persuaded many embedded-system engineers that digital-signal processing is a difficult discipline. This perception has its roots in the architectural and programming demands of first-generation DSPs, which were most often designed to implement digital filters. But before getting involved in a DSP-versus-microcontroller debate, you may ask, why use digital filters? What else are DSPs good for? The classic justification for digital filtering is that you can implement a linear-phase, FIR (finite-impulse-response) filter that preserves signal fidelity in applications such as audio processing. Avoiding signal distortions due to the unequal group delays that result from nonlinear phase-versus-frequency response characteristics can also be essential when you're trying to process sensor signals. As anyone who has tried knows, building a linear-phase filter in analogue technology is next to impossible; by comparison, a DSP and software-filter toolbox makes such realisations trivial.
If you use simulation tools for control-system modelling, you know that tools such as Matlab and Simulink from The Mathworks also model DSP algorithms and automatically generate code that you can port to a variety of hardware targets. But digital-signal processing's abilities really start with filter applications. For example, software tools also painlessly implement FFTs (fast Fourier transforms). You can then perform a frequency analysis on a snapshot of a continuous-time signal. This ability can help isolate a characteristic frequency from a sea of noise, such as detecting detonation in a car's cylinder head by screening microphonic noise from a piezoresistive knock sensor. Elsewhere, you might use an FFT to scan the characteristic frequency emissions of a rotating machine—to detect, say, the onset of a bearing failure in a helicopter's power train. DSPs also come into their own for applications such as sensorless, variable-speed-ac-motor control, in which you need to rapidly and sequentially compute the vectors that control power delivery. And, if you have a large number of sensor outputs to process to derive critical real-time control responses, a DSP is often the only answer. For example, today's Williams' Formula 1 car closely couples a Texas Instruments DSP with a Xilinx FPGA to form the core of its vehicle-control and -monitoring unit, which controls gear changes and traction-control tasks and logs around 220 sensor channels at maximum data rates of 1 kHz.
Starter kits develop confidence
If you're approaching digital-signal processing for the first time, you'll probably want more background information (see sidebars "First steps toward DSP" and "Architecture speeds real-time delivery"). But reading about products is no substitute for trying them, and starter kits provide an easy way to gain experience. The DSP family that today most resembles a microcontroller is Motorola's DSP56F800, which primarily targets real-time control applications. For example, the F805 core comprises a 16-bit fixed-point engine that operates on a dual Harvard architecture to allow three simultaneous accesses to program and data memory (Figure 1).
Two 36-bit accumulators serve the data ALU and its 16-bit MAC (multiply-accumulate) and barrel-shifter units. On-chip flash memory includes 31.5k words of program code, 4k words of data, and 2k words of boot code. There are also 2k words of data and 512 words of program RAM. The external memory interface addresses 64k words each of data and program memory. Peripherals include two four-channel, 12-bit ADCs; two six-channel PWM modules; two quadrature decoders and two timer modules that can operate concurrently by sharing pins; two further timer modules; and serial connectivity that includes a single CAN 2.0B module. There are 14 pins of GPIO (general-purpose I/O), and you can optionally redirect many resources, including the SPI and two serial-communications interfaces, to act as further GPIO. The 3.3V supply voltage powers the 2.5V core via an on-chip voltage regulator; all I/O is 5V-tolerant. Motorola's on-chip emulation technology provides in-system-debugging capability via a JTAG-standard port. The device comes in a 144-pin low-profile quad-flatpack, and the guide price is $13.20 (1000).
Development support comes from the DSP56F805EVM, which comprises a 130×165-mm pc board, the CodeWarrior IDE, and an SDK (software-development kit) for $299. The board carries the processor together with a 128k×16-bit SRAM for 64k words each of external code and data, an RS-232 port, and a parallel-port-to-JTAG interface that facilitates PC-based debugging. A quadrature-encoder/Hall-effect interface and dedicated motor-control logic facilitate applications such as servo control. Jumpers select different operational modes, and multiple headers break out signals and I/O for easy connectivity. The CodeWarrior IDE installs easily, but if you have another version on your PC, you may want to install this 30-day evaluation copy on another machine and thus circumvent Windows file-association conflicts. As you do for the IDE, you must register the SDK via the Web; at press time, Motorola was offering the normally $895 SDK for free and a full version of the normally $1195 IDE for $495. While you're on the Web, visit the product-summary pages for both the DSP56F805 and the SDK (MSW3SDK000AA); they are portals to a great deal of useful information.
CodeWarrior installs documentation that usefully includes the 56F805's hardware reference manual and data sheet, as well as instructions and reference manuals for the IDE. For a quick start, review the development board's online hardware manual and ensure that all jumpers are in their default positions. Next, connect the parallel interface to your PC and try the "Targeting DSP56F805" section of the online manuals. This area includes a brief tutorial that demonstrates how to create, compile, and link F805 code. By default, CodeWarrior uses "project stationery" to construct new projects. This approach automates creating and resolving dependencies between processor-dependent features, libraries, linker commands, and your code. If you're programming in C, the stationery also handles start-up-file creation to allocate and initialise system memory; optionally, you can select "empty project" and control these processes yourself. You can seamlessly mix-and-match C and assembler code within CodeWarrior's editor.
If you use the prebuilt stationery, the project window opens to reveal code, support, and library subdirectories; expanding any of these accesses the appropriate resource, which you can then edit. Select the "run" icon within the project window, and the default settings compile, link, and download the template program to the development board's external SRAM. The thread window opens, giving you a view of the stack, variables, and source code, together with execution controls, such as set/clear breakpoint, run, kill, and various step options.
Examine the available tools under the View menu, such as expression, global-variable, and register views. These facilities include raw-data, disassembly, source, and mixed-mode memory representations; you can also directly edit memory locations from here. If you now run the program, the console window greets you and reorders an array of numbers into successively higher values. The kill icon stops execution, ready for another compile-and-link session. You could, for example, try the simulator, which can report the number of machine cycles and instructions within a procedure. But you won't find a formal profiling tool, leaving you to calculate time-critical tasks. One alternative is to instrument your code at critical points by including calls to start and stop on-chip timers; removing the call overhead yields the true result. Of course, if your code runs without missing deadlines with the instrumentation in place, removing the overhead shouldn't negatively impact operation. Because significant performance differences can exist between on- and off-chip memory use, be sure to test the true target configuration.
CodeWarrior installs just one F805 example that detects interrupts from onboard switches to blink alternate LEDs. You can use this example as guidance for using C-compiler pragma directives, writing interrupt-service routines, and saving and calling library functions. You may now want to explore the SDK routines, but if you want CAN (controller-area-network) examples, you're out of luck—this capability is a $3000 option within the extra-cost premium package. Other premium capabilities include security routines, including RSA (Rivest, Shamir, and Adleman), DES (data-encryption-standard), and triple-DES algorithms, as well as telecom and speech-processing functions, such as the G711 voice coder. The SDK's CD-ROM includes the driver user's manual for these options, so you can see what's available. But you can access a range of free motor and motion-control examples, a variety of modem and telephony applications, and a plethora of tools and general-purpose routines. Notice that the SDK also demonstrates Motorola's specification for portable algorithm development, allowing third-party vendor support.
Other development tools include the $200 parallel-to-JTAG command converter; a USB-to-JTAG converter is currently in development. You can also specify the $1999 PCI-to-JTAG emulator connection and its $2999 Ethernet equivalent. At the other end of the spectrum—and possibly a better option for curious users who don't need the F805's I/O power—is the $65 DSP56F801 development kit. This kit also includes parallel-cable emulation, the SDK, and a free version of CodeWarrior that's limited to 16 kbytes of program memory; the unlimited IDE costs $495.
Multimedia lights up real-time control
Primarily targeting multimedia and portable equipment, Analog Devices' Blackfin family comprises three code-compatible processors that differ only in speed and on-chip memory complement. But these chips equally suit real-time-control applications with peripherals that include a UART, SPI and serial ports; timers with PWM and pulse-measurement capabilities; a real-time clock and watchdog timer; and a flexible, GPIO structure. Other system units include DMA and interrupt controllers, as well as hooks to control external flash memory and SDRAM (Figure 2). Video ports that support the ITU-R-656 format also simplify industrial machine-vision applications, as well as consumer/professional-video products that employ the 525/625-line component-video format.
Internally, the Blackfin core comprises a dual-MAC fixed-point processing engine that stores results in two 40-bit accumulators. In use, the VisualDSP++ IDE's compiler automatically synthesises floating-point operations in software using a default 32-bit-"long" value that best suits the core's architecture; you can optionally change this behaviour to comply with ANSII-C specifications. The core supports operations on signed or unsigned integer data via two 40-bit ALUs and a 40-bit shifter that perform traditional 16- and 32-bit arithmetic and logical operations. This 40-bit length supports rounding and saturation following repeated MAC cycles. There are also four video ALUs that accelerate processing via functions such as byte-alignment and packing operations, 16- and 8-bit additions with clipping, and 8-bit averaging and subtract/absolute-value/accumulate instructions. The ADSP-BF533 chip that ships with the starter kit is a top-of-the-range, 600-MHz version that packs 148 kbytes of memory into its 12-mm-sq, 160-pin, 0.8-mm-pitch BGA package. Guide prices range from $7 (1000) for the 300-MHz chip to $23.50 (1000) for the 600-MHz version.
Available now for $295, the ADDS-BF533-EZlite starter kit includes a 127×178-mm pc board that carries the processor, 2 Mbytes of flash, and 32 Mbytes of SDRAM. Onboard peripherals include an AD1836 audio codec with four input and six output channels; an ADV7171 video encoder and ADV7183 decoder, each with three phono jacks; an ADM3202 RS-232 line driver/receiver for the on-chip UART that's wired to a DB9 connector; an expansion interface that carries I/O, such as the parallel interfaces, serial interfaces, and SPIs; a JTAG in-circuit-emulator header; and various LEDs and pushbuttons. The package relies on a 20-kbyte, code-limited version of the VisualDSP++ IDE for program development. Debugging communications employ the onboard USB-to-JTAG debugging interface, which permits nonintrusive communications with a host PC via the environment's background-telemetry-channel. Documentation includes the evaluation-system manual, and a CD-ROM includes device data sheets and references, such as the programming manual; optionally, you can order printed versions from the vendor's Web site.
Ignore the quick-start card; follow the instructions in the evaluation-system manual, and the VisualDSP++ IDE installation proceeds faultlessly. (You must have the starter kit connected to avoid "invalid-licence" errors.) Notice that you'll need Windows 98/2000/XP; the software doesn't support NT, because NT doesn't natively support USB. Familiarise yourself with the CD-ROM's contents, and then try the tutorial from the wealth of potential paths that follow.
The first two exercises introduce how a basic component, such as the linker, interacts by having you build, run, and modify a procedure that calculates each sum of three products from fixed data arrays. Interestingly, the "mixed"-control view in the C-source window allows you to simultaneously compare C and assembler implementations of the routines. This facility is an alternative approach to some IDEs' ability to drag a source line into an assembler widow or vice versa to locate the corresponding code fragment. Other editor features allow setting and clearing of breakpoints, enabling line numbering, and setting bookmarks. If you load the code example in lesson three into the previous session, you can see various facets of the IDE's data-visualisation capabilities, such as normal plots, their FFT equivalents, and a FIR-filter-response analysis. Because this and other current Blackfin examples target the 535 processor, change the target to 533, or you'll encounter load-error failure messages. Giuseppe Olivadoti of the Blackfin tools marketing team says that Analog is porting all 535 examples to suit the 533.
Because the kit licence doesn't permit simulator sessions, download the full software and its evaluation licence, together with the licence-manager utility. Running this 60-Mbyte combination upgrades your installation; after 90 days, it reverts to the original restrictive version. After selecting the single-simulator session option, you can now see the linear-profiling simulation tool that analyses where the processor spends time within an application. Double-clicking on a routine shows the underlying assembler, together with the percentage of time spent within the flow; double-clicking on a program-counter entry highlights the corresponding disassembler output. Olivadoti explains that the profiler allows you to run the whole application in the profiling environment, rather than just one function at a time, although running one function at a time is possible. "Once the application is loaded, the profiler engine and a patented feature of the hardware displays the percentage and total execution count information about the application without inserting any wrapper code around the application," he says.
Software-profiling tools typically insert intrusive "wrapper code" at the head and the tail of a function to obtain statistics. VisualDSP++ dispenses with this overhead by taking a statistically random sample of the PC counter to record instruction addresses, derive execution statistics, and reveal code bottlenecks. Olivadoti also remarks that the simulator has several sophisticated and differentiating features, such as cache and pipeline visualisation. Because these features offer so much detail, Olivadoti notes, they are "simulator-only features." He says that, at this level, it's currently impossible to unobtrusively interrogate a processor at full speed without adding "a ton of logic and testing pins to the part."
The ADSP-BF533 folder that the environment creates during installation includes a number of 533-specific examples that you can use as templates for further development. Each includes a readme.txt file that describes functions and execution details. One major obstacle for newcomers is the C programmers' propensity for hiding essential components, such as header files, and obscuring their interactions; the good news is that the examples that accompany this kit are crystal-clear. You'll also encounter VSCE (VisualDSP++'s component-software-engineering) modules, which are preconfigured routines written to Analog Devices' VCSE standard. This approach allows you to add conformant modules from Analog Devices and third-party vendors to your own projects without fear of contentions, such as memory or I/O clashes.
However, the performance monitor that the kit's documentation describes won't appear in the menu system until you upgrade to the full version. You'll also notice that the environment is sluggish, due to the background-telemetry-channel agent that gathers information as the processor runs. Permanently overcoming this and other restrictions will cost you around $4000 for either the USB or the PCI-bus emulators, plus $3500 for the full software licence. But you'll no doubt explore the depth of the online documentation during your experiments, which will provide a taste of the power that the unrestricted product offers. For example, there's a useful section on porting the IDE to new and custom hardware environments. Also, don't forget to revisit the vendor's Web pages, where you'll find facilities such as updated information, a DSP user's community, and many more code examples.
1-GHz power speeds concurrent I/O
If you have the taste for experimentation, you may wonder what's involved in tackling a truly complex processor, such as Texas Instruments' TMS320C6000 family, which usefully offers code compatibility between fixed- and floating-point derivatives. A new starter kit showcases a 600-MHz version of the 16-bit fixed-point 6416, which follows the vendor's 256-bit very-long-instruction-word model. This top-end machine targets I/O-intensive applications, such as communications infrastructures. For example, the chip packs an ATM (asynchronous-transfer-mode) interface into its 532-pin, 0.8-mm-pitch BGA outline, which measures just 23 mm sq; other communications peripherals include Viterbi and turbo-decoder coprocessors. General-purpose peripherals comprise one 16-bit and one 64-bit external-memory-interface port; a 64-channel DMA controller; three multichannel, buffered serial ports; three 32-bit timers; a port that's selectable between PCI (peripheral-component-interconnect) and HPI (host-processor-interface) operation; and 16 bits of general-purpose I/O (Figure 3). With this amount of potentially concurrent I/O, you might need the vendor's forthcoming 1-GHz processor. But, thanks to a common code base, you can develop using the 6416 and target another, less I/O-capable family member. For example, the base 6411 chip omits the communications coprocessors to reduce cost from the 6416's $145 (1000) to $53 (1000).
Manufactured by Spectrum Digital, the starter kit comprises a 115×225-mm pc board that carries the DSP, a TLV320AIC23 codec, 16 Mbytes of SDRAM, 512 kbytes of user flash, and a USB-to-JTAG emulation port—all for around $395. Four 3.5-mm stereo I/O ports connect with the codec; some simple user- I/O ports connect to a bank of four LEDs and piano-key switches; high-density expansion connectors provide additional memory, peripherals, and PCI/HPI connectivity; and two port options provide external emulators. Despite the hardware's complexity, user-friendly software showcases Texas Instruments' eXpressDSP philosophy for modular software development. Ideally, eXpressDSP abstracts applications well enough that nonprogrammers can build applications by combining off-the-shelf algorithms within an execution template. In practice, you need sound C-programming experience to maximise the power that's available to you.
The core of eXpressDSP is the DSP/BIOS kernel, a real-time scheduler that comprises various modules to handle interrupts, pipes for streaming data, and periodic events. In effect, DSP/BIOS forms the basis of an RTOS that supports the 320C family. The Code Composer Studio IDE has a DSP/BIOS configuration tool that lets you pick which modules to include at program compilation time, thus minimising the firmware's memory footprint. Crucially, each DSP/BIOS module includes code instrumentation that permits Code Composer to debug running applications via the USB-emulation link. For minimum impact on real-time operation, the instrumentation runs when the DSP chip is in its idle state between executing code threads. You can view the execution graph as it switches between threads in a graphical format that helps reveal missed deadlines (Figure 4). Other tools that ease time-critical task analysis include a CPU load graph and a statistics window that reports a thread's average- and worst-case execution times. You can also pipe in data from a PC-resident file, such as the output from a DSO that represents a real signal you want to process. DSP/BIOS provides a well-defined set of APIs that apply across the entire 320Cxx family, so you can easily port code between alternative platforms. By banning direct access to peripherals and insisting upon re-entrant, relocatable code, the eXpressDSP algorithm standard permits easy integration of compliant algorithms from Texas Instruments and third-party vendors. You can download a free DSP/BIOS driver-development kit.
You can also freely download a set of three reference-framework applications as "starterware" for most of TI's starter kits. Comprehensive application notes describe the capabilities of these models, including examples of how to customise them. RF1 targets approximately 3.5k-word-footprint applications that require one to three channels and a similar number of eXpressDSP algorithms. Limitations include no support for dynamic memory allocation, thread pre-emption, blocking, multirate operation, or control functions. For these reasons, RF1 best suits lower end 5xxx hardware platforms. The midrange RF3 typically suits 6xxx chips that run one to 10 channels and one to 10 algorithms. The RF3's approximately 11k-word footprint provides all of the facilities missing from RF1 except task blocking. Finally, the RF5 version provides all such facilities, together with support for more than 100 channels and algorithms, at the cost of some 28k words of memory. RF5 enhancements include a separate thread for multiprocessor support.
Your starter kit may include an eXpressDSP for Dummies booklet, which targets first-time users. At press time, the RF3 application that this booklet studies was unavailable for the 6416 starter kit. But an e-mail to Elizabete de Freitas, a DSP-software field-application engineer for TI Germany, produced a port within a few hours—suggesting that C programmers should have little difficulty in tailoring reference-framework applications to new environments. RF3 describes a two-channel audio-processing chain, in which alternate channels include highpass and lowpass FIR filters with independent volume controls. You first learn how to build and run the application using, for example, a PC's CD-ROM and sound card. The booklet then describes the internal structure of the sample application; core components, such as header files, include comprehensive documentation. Finally, you get to modify the application to produce a mono audio-recorder/player. You start by removing one channel to leave mono sound that's either highpass- or lowpass-filtered. In practice, the RF3 application-note instructions don't quite work, but the debugging environment helps you by highlighting errors and warnings in red; double-clicking on an error takes you directly to the offending line in the appropriate file. Exercises also present important tools, such as the execution graph. An unlimited version of Code Composer Studio costs $3595, including one year's maintenance; Spectrum Digital's XDS510 USB emulator adds $1995.
For more information...
For more information on products such as those discussed in this article, contact any of the following manufacturers directly, and please let them know you read about their products in EDN Europe.
Agere Systems
www.agere.com
Analog Devices
www.analog.com
Forward Concepts
www.fwdconcepts.com
Infineon Technologies
www.infineon.com
Intel
www.intel.com
The Mathworks
www.mathworks.com
Motorola Semiconductors
www.mot-sps.com
Spectrum Digital
www.spectrumdigital.com
Texas Instruments
www.ti.com
Xilinx
www.xilinx.com
