FROM EDN EUROPE: RISC/FPGA blend offers new take on reconfigurability
By Graham Prophet -- EDN, May 13, 2004
The S5 microprocessor architecture from start-up Stretch offers a new variant on configurable computing, representing an option that, according to chief executive officer Gary Banta, "has never been tried before." The chip comprises a conventional Xtensa processor core from Tensilica with an array of programmable elements.
It differs from other combinations of CPUs-plus-FPGAs in that it organises the programmable logic as a block of programmable hardware that is inside the datapath of the processor. The result is a RISC machine with new instructions that match the processing demands of the application but without the overhead of accessing a conventional coprocessor structure.
You program the device, both in writing the code for your application and in configuring the hardware elements, in a single tool flow, writing in C/C++. Banta claims that the architecture is both flexible enough to address a wide range of computationally intensive applications and powerful enough to be cost-effective; a single device can achieve tasks that previously might have required a multiprocessor array.
The programmable part is called the ISEF (instruction-set-extension fabric). Because it is much less general-purpose than standard FPGA, it is denser in logic functions per unit area. For now, however, Stretch is disclosing neither the density nor the amount of programmable logic. It is also not revealing the area mix of core-to-FPGA ratio.
Beginning with an application in C/C++, the code undergoes a fairly conventional profiling exercise to identify the computationally intensive loops. Having identified those sections, the compiler then converts the code embodied in them to configuration code for the ISEF logic, so that, as far as the rest of the program is concerned, that code has been compressed to a single instruction.
It addresses the ISEF via three 128-bit-wide paths to a register file that is tightly integrated to the core and can be configured to provide wide, parallel datapaths; all of the data is therefore close to the execution unit, which is efficient in both timing and power. The company describes the process of compressing the critical code and creating a configuration as automatic, but you do get involved in optimising the configuration. How do you know when you have an optimal solution? Banta says that when you achieve a setup for the ISEF that "touches" the data just once—takes it, operates on it, and returns a result—then you know you have completed the process.
You can configure the ISEF once at boot-up with all the operators you need, making it many operators wide and deep. Or, you can load it on the fly with operators as they are required. You can perform these tasks or use a cache-type mechanism; Banta claims that the overall efficiency of the device is so high that an occasional "cache miss," causing an operator to be loaded, would in most cases not be a problem. Claimed compilation is on the order of a few minutes to "fill" the ISEF. Stretch claims it takes around 100 µsec to load a new ISEF configuration.
Stretch has produced EE-MBC (EDN Embedded Microprocessor Benchmark Consortium) results on the "Telemark" suite that show that the optimisation process (coding the hardware) increases the performance by more than 200 times. More significantly, says Banta, the processor at 300 MHz outperforms "pure" DSPs running as fast as 720 MHz on the same application code. That more-than-200-fold performance gain is specific to the EEMBC code, but any computationally intensive code set should achieve similar performance gains.
Banta cites three circumstances under which you might be able to apply his concept: when you are forced into using multiple processors, when you are forced into using standard processors with high-performance coupled FPGAs to offload processing of key functions, or when you have to build complex ASICs.
A range of S5 parts vary in I/O capability, depending on market and range in price from $35 (25,000) for typical consumer applications to about $100 (10,000) for telecom, networking, military, and security applications. Power will be 1 to 3W, so Banta does not recommend using this processor for a "shirt-pocket product." Instead, he notes, the company has "concentrated on speed and performance." You can find software-evaluation tools on the company's Web site, and hardware delivery will start in the third quarter of this year.
Stretch, +1 650-864-2700, www.stretchinc.com.
