2003 DSP directory

By Robert Cravotta, Technical Editor -- EDN, April 3, 2003

DSP shipments were tracking at 5% growth for 2002 until shipments in December ballooned. According to market-research company Forward Concepts (www.forwardconcepts.com), this balloon in shipments netted an overall DSP-revenue growth of 14.1% for 2002. Wireless applications, commanding 65.8% of DSP dollars in 2002, remain the market movers for DSP shipments this year. Forward Concepts predicts that semiconductor-market growth this year will not be “above normal” and forecasts a 20% growth for the DSP market for 2003.

Despite some vendors withdrawing from the DSP market over the last year, this year’s directory contains more entries than ever before. StarCore began its existence as a stand-alone company late 2002. The directory no longer lists some products from the member companies of the technology center, such as Agere’s StarPro2000. Also, the design team for the Carmel DSP core is now part of StarCore, and the Carmel core is no longer available for licensing. Another DSP-core-design-team move means you can find last year’s DSP Group family of cores in the directory under ParthusCeva.

To maintain a clear distinction between DSP and controller devices, the directory survey requested devices, cores, or extensions that not only can process signals, but also find primary use in signal processing. The DSPs have to be software-programmable devices, cores, or extensions that include an assembler or a compiler in the tool set. This stipulation eliminates products that, although they may include a programmable DSP core, restrict users to only selecting and setting operating parameters. Also, listed devices or intellectual property must be currently or soon available. Even with these criteria, the directory still grew.

The directory lists entries alphabetically by vendor and consolidates the development-support section in the last entry for each vendor’s section. This structure reduces the amount of duplicate information, and, more important, it emphasizes that tool sets are usually common across a vendor’s product lines. Almost without exception, integrated tool sets are a strategic element of any DSP offering and play a large role in design wins. The directory index groups entries by processor size rather than directory location to facilitate the comparison of similar-sized processors. (This page contains devices A through L; click here to see devices M through Z.)

Contact Technical Editor Robert Cravotta at 661-296-5096, fax 661-296-1087, e-mail rcravotta@edn.com.

 

 

ADELANTE TECHNOLOGIES SATURN

at a glance:

• The core area measures 0.5 mm² and consumes 0.25 mW/MHz in a standard 0.18-micron CMOS process.

• The Saturn can perform 420 MMACs (million MACs)/sec at 210 MHz.
  

Adelante’s Saturn is an extensible, low-power, small-area, “open” DSP core and subsystem targeting wireless-baseband handsets and digital-control applications. It employs a dual Harvard architecture with two 16-bit multipliers, four 16-bit ALUs that can combine into two 40-bit ALUs (32 bits with 8 bits of overflow), a shift-and-saturation unit, a bit-manipulation unit, a barrel shifter, a hardware-loop-control unit, a program-control unit, and two data memories that are configurable to 64k words and expandable to 1M word with paging. The designer extends the core via custom application-specific instructions, execution units, and coprocessors to accelerate repetitive tasks.

The Saturn core integrates into Adelante’s Lunar DSP subsystem, which includes program and data memory, DMA, interfaces to external processors, peripherals, and I/O (including an AMBA bus for ARM and MIPS processors); BIST; and JTAG hardware-debugging capability. Special constructs in the three-stage pipeline enable single-cycle-overhead short branching and zero-overhead long branching. One nonmaskable and 16 maskable interrupts with single-cycle interrupt switching and simultaneous shadow X/Y-address pointer switching support immediate execution of service routines.

Addressing modes: The Saturn supports single- and dual- data-memory-operand addressing for 32-bit operands, with direct data and absolute addressing. Offset, indirect, absolute, immediate, modulo, and bit-reversed addressing support bit/nibble/byte access to memory. Two of the three X/Y-address pointers are context-sensitive.

Special instructions or integral-peripheral functions: Designers can extend the Saturn’s 16-bit instruction set with 256 application-specific 96-bit VLIW (very-long-instruction-word) instructions that can fully exploit all core resources in parallel to accelerate repetitive DSP functions (for example, two-cycle execution of a 12-operation Viterbi butterfly). Designers can also integrate application-specific execution units and coprocessors into the DSP subsystem to accelerate computationally intensive functions, such as turbo coding or multichannel ADPCM (adaptive differential pulse-code modulation).

Development support: The Atmosphere development environment supports code-development debugging for application-specific instructions and execution units. The code-development tools include a compiler, a linker, a debugger, an instruction-set simulator, and a profiler. The debugger supports use with a JTAG hardware debugger and the runtime-debugging block for in-circuit runtime emulation. Adelante offers design services for the development, integration, and verification of application-specific execution units and application-specific coprocessors.

AGERE SYSTEMS DSP16XXX

at a glance:

• The DSP16410 can perform 800 MMACs (million MACs)/sec at 200 MHz.

Agere’s DSP16210 and DSP16410 devices use the DSP16000 core and target digital-communications applications that benefit from large, on-chip RAM with downloadable system support. The DSP16210 includes 60k words of dual-port RAM and can address as many as 192k words of external storage in both its code/coefficient-memory address space and data-memory address space. An internal boot ROM includes system-boot code and hardware-development system code. This device also contains a bit-manipulation unit; a two-input, 40-bit ALU with add/compare/select for enhanced signal-coding efficiency and Viterbi acceleration; and a three-input adder for single-cycle accumulation of the results of both multipliers. To optimize I/O throughput and reduce the I/O service-routine burden on the DSP core, two modular I/O units manage the simple serial-I/O port and the 16-bit parallel host-interface peripherals. They also provide transparent DMA transfers between the peripherals and on-chip, dual-port RAM.

The DSP16410 targets communications-infrastructure applications and features twin DSP16000 dual-MAC (multiply-accumulate) DSP cores and enhanced DMA capabilities. Each DSP core has access to a 192-kbyte block of memory (384 kbytes total) and share a 4-kbyte block of memory for interprocessor communications. The DSP16410’s large on-chip memory supports fixed-point signal-processing functions, including equalization, channel coding, compression, and speech coding. A centralized DMA unit supports transparent peripheral-to-memory and memory-to-memory transfers. The DSP16410 includes a 16-bit parallel port with DMA support that can provide host access to all DSP memory. The two serial-I/O units also include DMA support, are compatible with TDM highways, and include hardware support for u- and A-law companding.

Addressing modes: The DSP16000 core architecture supports immediate, register-direct, address-register-indirect, and program-counter-relative modes, as well as register-plus-displacement addressing, and circular-buffer addressing.

Special instructions or integral-peripheral functions: The special instructions are arithmetic, logical, and shift operation, and bit-manipulation instructions to implement nonlinear algorithms, such as signum, A- and u-law conversions, half- and full-wave rectification, and rounding. The bit-manipulation instructions include barrel shifting, normalization and exponent computation, and bit-field insertion or extraction.

Development support: Agere’s LUxWorks supports development for DSP16000 devices. The integrated system-level development tools include a C compiler, an assembler, a linker, and a simulator. Hardware-development platforms and in-circuit-emulation capabilities are available through Agere’s TargetView JTAG communication system, featuring Agere’s DART (Data Access in Real Time) for real-time data collection. Agere also provides optimized libraries for voice transcoding and echo cancellation for wired networks and 2, 2.5, and 3G wireless standards.

ANALOG DEVICES ADSP-21XX

at a glance:

• All ADSP-21xx processors are source-code-compatible.

• Devices cost less than $4 in high volume.

All ADSP-21xx processors are source-code-compatible and feature a high-level algebraic programming syntax. All instructions, including multifunction instructions, execute in a single clock cycle. ADSP-21xx processors use separate program and data buses operating on 24-bit instructions and 16-bit data. The wider instruction word allows the device to use a more complex and robust instruction set than a 16-bit operation code, and the 16-bit data word provides lower power consumption for the necessary dynamic range. These processors include as much as 2.4 Mbits of on-chip SRAM and integrate a programmable DMA controller to maximize I/O throughput. The ADSP-218x supports as much as 4 Mbytes of external memory, and the ADSP-219x architecture supports 16M words of external memory. All processors support a variety of serial-communications interfaces to ADCs, DACs, and other processors.

Addressing modes: ADSP-21xx processors support immediate, register-direct, memory-direct, and register-indirect addressing modes. The ADSP-219x adds register, indirect-post-modify, immediate-modify, and direct- and indirect-offset addressing modes. Each address generator supports as many as four circular buffers, each with three registers. The ADSP-219x supports as many as 16 circular buffers using a data-address-generator shadow-register set and a set of base registers for additional circular-buffering flexibility.

Special instructions or integral-peripheral functions: The ADSP-21xx contains dedicated loop hardware and a “do-until” loop instruction that supports loops ranging from 0 to 16,000 iterations, or loops, with infinite iterations. The ADSP-218x supports four-deep nesting via its loop hardware, and the ADSP-219x supports as many as eight loops. In addition to the standard arithmetic and logic instructions, the ALU supports division primitives. The ADSP-219x program-sequencer features a six-deep pipeline and supports delayed branching. The ADSP-219x buses and instruction cache provide the data flow to maintain a continuous execution rate.

ANALOG DEVICES ADSP-21XXX SHARC

at a glance:

• Devices natively support 32-bit fixed, 32-bit IEEE floating, and extended 40-bit floating-point data types.

• Multiprocessing configurations require no glue hardware.

The ADSP-21161N is the latest member of the SHARC family of general-purpose programmable DSPs. It uses a Super Harvard Architecture and has both SIMD (single-instruction-multiple-data) and SISD (single-instruction-single-data) functions. Each of the two computational blocks in the SHARC SIMD core includes a multiplier, an ALU, a data-register file, and a barrel shifter that can process in parallel in SIMD mode. The core contains dual data-address generators, independent data- and address-memory buses, a program sequencer with zero-overhead looping, an instruction cache, and a timer. While the core operates at full speed, the I/O processor moves data on and off chip. SHARC DSPs integrate 1 Mbit to 4 Mbits of on-chip SRAM; as many as four serial ports, six link ports, and 14 zero-overhead DMA channels; an SPI-compatible port; a synchronous-DRAM controller; a parallel host interface; cluster multiprocessing support; and an IEEE JTAG standard 1149.1 test-access port with on-chip emulation. The two independent, on-chip, dual-ported SRAM blocks are selectable between program and data memory. The independent synchronous serial ports operate in TDM multichannel mode and, on the ADSP-21065L and ADSP-21161, offer I²S mode, which is useful for audio applications.

Addressing modes: ADSP-21000 SHARC DSPs support absolute and relative-direct addressing, premodify and postmodify registering, immediate-value-indirect addressing, and modulo and bit-reverse addressing. The dual-ported memory allows independent data transfers from the core and the I/O. Three on-chip buses allow two data transfers from the core and one from I/O in one cycle.

Special instructions or integrated-peripheral functions: The ADSP-21000 SHARC family features distributed on-chip bus arbitration. These devices allow you to connect as many as six processors (two for the ADSP-21065L) in parallel, plus a host. All SHARC instructions execute in one cycle. Special instructions include bit manipulation, division iteration, reciprocal of square-root seed, conditional subroutine call, single and block repeat with zero-overhead looping, average of two numbers, bit packing and unpacking fixed to and from floating-point conversion, and conditional execution of most instructions. SHARC supports IEEE-754 single-precision floating-point, 32-bit fixed-point, and a 40-bit extended IEEE format for additional accuracy.

ANALOG DEVICES ADSP-215XX BLACKFIN

at a glance:

• System architecture supports an integrated DSP and RISC microcontroller-unit instruction set.

• Dynamic power management minimizes power consumption for power-constrained applications.
  

Blackfin DSPs feature dual-MACs (multiply-accumulate) units, 300-MHz clock rates, and dynamic power management for balancing system performance and power consumption. The modified Harvard architecture core combines signal- and control-processing features into a single instruction-set architecture that benefits programming in high-level languages, such as C/C++. DSP-core functional blocks and capabilities include two 16-bit MAC units, two 40-bit ALUs, four 8-bit video ALUs, and a barrel shifter, plus eight 32-bit math registers with support for 8/16/32-bit integer and 16/32-bit fractional data types. The four 8-bit video ALUs address multimedia algorithms including MPEG-2, MPEG-4, and JPEG, allowing one device to concurrently process audio, video, imaging, and data information. The ADSP-21535 targets next-generation digital-communication systems and Internet appliances, and the ADSP-21532 targets consumer multimedia systems.

Blackfin DSPs support user and supervisor modes, byte addressing, memory protection, and an orthogonal RISC instruction set. All Blackfin DSPs support a hierarchical and configurable memory model. L1 memory is physically closest to the core for highest system performance and is configurable as either SRAM or cache. L2 memory provides a larger memory space suitable for bulk storage of instructions or data. Additionally, dynamic power management permits context-sensitive control over power consumption by enabling designers to dynamically vary both the operating frequency and voltage of the DSP core for optimizing power-consumption profiles.

Addressing modes: All Blackfin devices support DSP and general-purpose addressing modes, including indirect, indexed, autoincrement or autodecrement, postautoincrement, and bit-reversed. Four sets of index, base, length, and modify registers enable circular (modulo) buffering of as many as four buffers per data-address generator. In addition, eight 32-bit registers are available for general-purpose addressing of 8-, 16-, and 32-bit data.

Special instructions or integral-peripheral functions: The Blackfin instruction set includes special instructions for video and next-generation communications algorithms. Video-pixel-manipulation instructions include quad-byte operations for sum-absolute difference, average, and pack/unpack. Communications algorithms use dual-MAC instructions with rounding and saturate options in addition to add/compare/select or vector operators.

ANALOG DEVICES ADSP-2199X

at a glance:

• Processors target mixed-signal, embedded-control, and signal-processing applications.

• Devices integrate a 160-MIPS DSP with a 14-bit, 20M-sample/sec ADC.

The ADSP-2199x family encompasses high-performance, mixed-signal DSPs that maintain full code compatibility with ADSP-219x processors. These devices integrate mixed-signal components, such as high-resolution ADCs, with a variety of peripheral components to form single-chip devices targeting embedded-signal-processing and -control applications, such as industrial measurement and control, high-end servo-motor drives, uninterruptible power supplies, high-end switched-mode power supplies, optical-networking control, and intelligent-sensor interfaces.

The ADSP-21990, ADSP-21991, and ADSP-21992 integrate a 16-bit ADSP-219x core, operating as fast as 160 MHz, with a 4k- to 32k-word program memory; a 4k- to 16k-word data memory; and an eight-channel, 14-bit, 20M-sample/sec ADC core, with dual S/H amplifiers for simultaneous sampling. An external memory interface enables direct access to as much as 1M word of external memory for program-memory expansion, data-memory expansion, or both. ADSP-2199x devices are available in industrial- and automotive-temperature (ADSP-21992 only) ranges and packaged in both MBGA and LQFP versions.

Addressing modes: Identical to the ADSP-219x products, the ADSP-2199x products support immediate, register-direct, memory-direct, register-indirect, indirect-postmodify, immediate-modify, and direct- and indirect-offset addressing modes. The ADSP-2199x supports as many as 16 circular buffers using a data-address-generator shadow register and a set of base registers for additional circular-buffering flexibility.

Special instructions or integral-peripheral functions: ADSP-2199x devices share all of the architectural features and special instructions of the ADSP-219x core. The key integrated peripheral of these products is the high-performance, 14-bit ADC. The embedded-control peripherals include a three-phase PWM generation unit; a 32-bit incremental-encoder interface; dual auxiliary PWM outputs; a watchdog timer; and general-purpose peripherals, such as timers, digital I/O lines, and serial-communications and programmable-interrupt controllers. Additionally, these devices include an on-chip precision-voltage reference and an integrated power-on-reset circuit.

ANALOG DEVICES ADSP-TS101 TIGERSHARC

at a glance:

• TigerSHARC can perform 1500 Mflops or 2000 16-bit MMACs (million MACs)/sec at 250 MHz.

• The device targets wireless-infrastructure and multiprocessing applications.

The ADSP-TS101S TigerSHARC DSP is a floating-point DSP targeting multiprocessing and 3G wireless-infrastructure applications. This static superscalar architecture blends the best features of DSP, RISC, and VLIW (very-long-instruction word) for a high-performance DSP architecture. These features include a load/store architecture, branch prediction, a large interlocked register file, fast mathematical computations, bit reversing, zero-overhead looping, background data movement with DMA, and an instruction width that varies from one to four words. Two computational blocks in TigerSHARC devices support 1-, 8-, 16-, and 32-bit operations. Each computational block contains a 32-entry register file, an ALU, a multiplier, and a shifter. It can execute two 32-bit floating-point MACs (multiply accumulates), eight 16-bit MACs with 40-bit accumulation, or two 16-bit complex MACs in one cycle. The device can perform as many as 32 mathematical operations per cycle with 8-bit data types. Three 128-bit buses support TigerSHARC’s three on-chip memory banks, which total 6 Mbits. In a given cycle, the processor can fetch four 32-bit instruction words and load 256 bits of data into the register file or store it in memory.

Addressing modes: TigerSHARC has two integer ALUs in addition to the two computational blocks. It uses the ALUs primarily for data-address generation, and each unit contains a 32-bit ALU and a fully orthogonal 32-word register file. These units can generate an address per cycle that allows the device to send two 128-bit words to each computational unit. These units also support preaddress and postaddress modification, circular buffering, and bit reversing without an extra-cycle penalty.

Special instructions or integral-peripheral functions: Special instructions to accelerate both symbol- and chip-rate processing for 3G baseband-signal processing, include a complex MAC operation for chip-rate processing and add/compare/select operation for channel-decoding algorithms. Peripherals include four bidirectional link ports, a 14-channel DMA controller, and a 64-bit-wide external port that includes an SDRAM controller, a host interface, and support for glueless multiprocessing of as many as eight TigerSHARCs. The four link ports are bytewide interfaces that transmit data on both the rising and the falling clock edge and offer a second method for multiprocessing with ring and 2-D mesh multiprocessing configurations.

Development support: The CrossCore development components include the VisualDSP++ software-development environment, EZ-Kit Lite evaluation systems, emulators, and DSP/math libraries. VisualDSP++ is an integrated software-development environment that includes an assembler, a C/C++ compiler, a linker, a debugger, an archiver, a loader utility for creating bootable images, VDK (VisualDSP++ kernel), advanced plotting tools, and statistical profiling. The EZ-Kit Lite evaluation system supports extension by the addition of JTAG in-circuit emulation. Emulators are available for serial-port, PCI, and USB host platforms. The VisualFone is the development system for SoftFone-based products. A complete GSM/GPRS protocol stack for SoftFone is available from TTPCom.

ARC ARCTANGENT

at a glance:

• Cores support a user-customizable instruction set, registers, buses, interrupts, caches and memories.

• You can integrate preverified peripherals, such as, USB 1.1 and 2.0, Ethernet media-access controller, and UART, using the ARChitect.

The ARCtangent-A4 and ARCtangent-A5 cores are synthesizable, user-customizable, 32-bit RISC processors with optional DSP extensions. Developers can add extension instructions, configure caches, integrate peripherals, and add DSP extensions with the ARChitect configuration tool, a graphical-design tool that generates RTL files and synthesis scripts. The ARCtangent-A4 uses a 32-bit instruction set, and the ARCtangent-A5 uses the ARCompact 16/32-bit instruction set that allows free mixing of 16- and 32-bit instructions for greater code density without mode-switching penalties. Both cores are synthesizable with industry-standard tools and are portable to almost any foundry or process. The integrated RISC/DSP cores allow programmers to use a single tool chain for RISC and DSP software development.

Addressing and processing modes: The ARCtangent supports as many as four banks of XY memories from 512 bytes to 16 kbytes and has a user-extendable register file. The address-generation units for the XY memories support modulo and bit-reverse addressing with variable-offset preincrement and postincrement modes.

Special instructions or integral-peripheral functions: DSP features include 16×16-, 24×24-, and dual 16×16-bit MAC (multiply-accumulate) operations with 8 guard bits for the accumulator, saturating addition and subtraction instructions, fractional arithmetic, normalize (find first bit), swap, minimum/maximum, 32×32-bit barrel shifter, 32×32-bit multiplier, and zero-overhead loops. The instruction set is conditional, with as many as 16 user-defined condition codes. Developers can also configure and extend the instruction set to optimize performance for specific applications.

Development support: The ARCtangent RISC/DSP comes with RTL source code, extensive documentation, the ARChitect tool, MetaWare C/C++ Compiler and SeeCode debugger, an assembly-language DSP-function library that is callable from C/C++ programs, customer training, and technical support. The single tool chain supports both RISC and DSP software development. ARC also provides preverified and integrated peripheral intellectual-property cores, including USB, Ethernet, and driver software; the Precise/MQX RTOS; network-protocol stacks; and software for vertical-market consumer and communication applications. Third-party support includes emulator support from Corelis (www.corelis.com) and Ashling Microsystems (www.ashling.com) with memory-system support from Denali (www.denali.com).

BOPS MANARRAY

at a glance:

• The core has power consumption of 11 to 36 mW for as many as 4000 MIPS.

• BOPS Halo Compiler achieves an EEMBC (EDN Embedded Microprocessor Benchmark Consortium) Telecom Benchmark score of 181.

The ManArray fully scalable, configurable, synthesizable DSP architecture is programmable and reusable in an array of implementations for communications, mobile-multimedia, and wireless applications. Each application-specific family balances the trade-offs in cost, power, and performance for targeted applications. The MoCARay configuration targets GPRS/EDGE (general-packet-radio-service/enhanced-data-rate-for-GSM-evolution) baseband layer 1 processing at less than 20 mW and turbo-codec processing at less than 50 mW for software-defined trimode 2, 2.5, and 3G handsets. The MICoRay configuration targets full-duplex MPEG-4 CIF codec processing at less than 100 mW for high-quality videoconferencing on Smartphones and PDAs. The WirelessRay configuration targets physical-layer processing for 802.11a, b, and g at less than 70 mW for wireless-LAN devices.

Addressing modes: The BOPS architecture supports SIMD (single-instruction-multiple data), MIMD (multiple-instruction-multiple-data) and SMIMD (synchronous-multiple-instruction-multiple-data) operation. A fully programmable, patternable, scalable DMA engine supports the addressing modes and data-flow management necessary to meet the computational requirements of the high-performance, scalable DSP cores.

Special instructions or integral-peripheral functions: Each family has an enhanced instruction set targeting mobile-wireless, mobile-video, or high-performance streaming media. You can easily integrate all functions—from a RISC coprocessor to a simple PCI interface—into BOPS SOCs (systems on chips).

Support: The BOPS software-development kit integrates tools for application-software programmers, SOC designers, firmware designers, and system architects into one development environment. The Jordan and Travis evaluation boards enable designers to evaluate the ManArray architecture and develop SOCs using the ManArray-based family of DSP cores. The BOPS Halo Parallelizing C-Compiler enables programmers to accelerate their software-development schedule by automatically exploiting the three levels of parallelism in the ManArray architecture, including packed data, processor arrays, and indirect VLIW (very-long-instruction word).

CHIPWRIGHTS CW4011, CW4511

at a glance:

• Devices can deliver 7500 MMACs (million MACs)/sec for less than 500 mW.

• The CW4511 includes peripherals targeting digital-camera applications.

The CW4011 visual-signal processor’s high-performance, low-power architecture targets digital-signal-processing algorithms for imaging data that uses an SIMD/VDIW (single-instruction- multiple-data/very-dense-instruction-word) architecture and integrates eight parallel DSP-execution units and one RISC processor on the same die. Each DSP unit can generate its own address into memory to maintain processing throughput. The DSP array performs parallel accesses to the 128-kbyte, multibank SRAM through a 128-bit bus. The CW4011 normally acts as the system controller but can operate as a coprocessor that connects to many 8- and 16-bit microcontrollers. You can chain together multiple CW4011s through the integrated video ports for a distributed-multiprocessor system for image-processing applications.

The CW4511 builds on the CW4011 by adding I/O capabilities, such as USB, LCD outputs, and triple DACs for NTSC or PAL outputs, targeting digital-camera applications. The CW4511 lets you implement a digital camera, including image-processing algorithms, memory control, and other housekeeping functions with just one VLSI (very-large-scale-integration) chip. The CW4011 and CW4511 can achieve 7500 million MACs (multiply accumulates)/sec at power levels of less than 500 mW at full frequency. These processors can achieve CIF-level MPEG-4 encoding at more than 30 frames/sec, VGA-level encoding at more than 15 frames/sec, and JPEG compression at more than 20 million pixels/sec.

Addressing and processing modes: This processor family offers special addressing modes, including strided and scatter-gather memory accesses, supporting narrow data applications, such as imaging. Each parallel processor in the chip can perform arithmetic operations on one 32-bit, two 16-bit, or four 8-bit slices in one instruction.

Special instructions or integral-peripheral functions: This processor family includes special instructions for imaging, including a dot-product and a sum-of-absolute-differences instruction. The 16-bit video-in and -out ports with 256-byte FIFO buffers support simultaneous data transfers at 50M words/sec. The CW4511 includes integrated peripherals including a USB controller, an LCD output, and triple DACs for output NTSC or PAL video.

Development support: Metrowerks’ (www.metrowerks.com) CodeWarrior integrated development environment supports development for the CW4011 and CW4511. These tools include an assembler, an ANSI C compiler, a linker, a simulator, and a profiler in an integrated, easy-to-use package. Because the user interface is identical to that of other products that CodeWarrior supports, engineers who have previously used CodeWarrior can immediately start using the ChipWrights version of this tool.

CIRRUS LOGIC CS494XX

at a glance:

• Support for AAC, DTS 96/24, and THX Cinema requires no additional external logic or memory.

Cirrus Logic’s CS49400 DSP family integrates a front-end, 24-bit DSP for audio-standard decoding and a 32-bit, back-end DSP for PCM postprocessing. It features a dedicated multistandard decoder; key peripherals; and X, Y, and program memories in a single chip targeting digital-entertainment applications, such as audio-video receivers, outboard decoders, DVD receivers, DVD-audio/video/SACD (Super Audio CD) players, and automotive-entertainment systems. The device can support multichannel DTS 96/24, Dolby Digital, AAC, and THX Ultra2 Cinema without additional logic or memory, and it supports customer software-security keys.

Special instructions or integral-peripheral functions: Along with dual S/PDIF (Sony/Philips digital-interface) transmitters and serial and parallel host interfaces, the CS49400 includes eight-channel audio- input with PCM-output channels as large as 24 bits.

Development support: The CS49400 features an audio framework, including customizable programming, certified audio decoders, and sound-enhancement programs for DTS 96/24, Dolby Digital, AAC, and THX. Cirrus’ software library provides legacy audio-decoder support.

CLARKSPUR CD2450 AND CD2480

at a glance:

• The CD2480 uses an open architecture to support additional instructions.

The configurable-processor CD2450 core has selectable datapath precision, register-set size, and interrupt structure. Memories may be on- and off-chip, ROM and RAM, and with different speeds and sizes. Peripheral-interface circuits support common functions and protocols, yet are configurable for the requirements of the application system. Clarkspur custom-designs all modules to fit together for a compact layout with minimum interconnection delays. All datapath elements are configurable to a precision of 16 to 24 bits. The multiplier is pipelined in two stages, producing a 31-bit product every 20 nsec with a latency of 40 nsec for new arguments in the X and Y registers. The ALU is full-function with double-word addition and subtraction with the 32-bit accumulator ACCH and ACCL. The shifter SHIFT covers a bytewide range of left logical shifts and one of right arithmetic shifts on the b ALU input register.

The two data memories contain two sets of four address-pointer registers. You can index the pointers, which loop in arbitrarily sized buffers. One register in each set can act as a stack pointer for program instructions. The stack in RAM0 handles interrupts. The three interrupts are part of the system-function portion of the core. They have a three-level priority structure, and you can use them internally with interface modules or with external system signals. The user-defined two inputs and two outputs also handle system signals through noninterrupt programmed transfers.

The CD2480, an enhanced version of the CD2450, targets audio-compression applications in which extensive floating-point operations may take place, such as AAC, MP3, and CELP (Code Excited Linear Prediction). The core maintains a conventional 16-bit instruction-bit width but adds a 24-bit-data-width architecture, a strong barrel shifter, a normalizer/denormalizer, an enhanced RAM-pointer-modification capability, a double- loop-repeat instruction, a one-cycle-pipelined multiply, and one-cycle operation in double-word instructions.

Addressing and processing modes: The CD2480 supports single- or double-word operation.

Special instructions or integral-peripheral functions: The core includes an optional Huffman Decoder instruction.

Development support: Clarkspur offers an assembler, linker, emulator, PC-based software debugger, and demo board. The emulator board on an FPGA runs only at low speeds (25 MIPS). Archelon (www.archelon.com) offers a META-C compiler that can use Clarkspur’s code tables for software development.

DSP ARCHITECTURES DSP24

at a glance:

• The device targets low-power, software-minimized, frequency-domain signal-processing applications.

• Strategic radiation-hardened and high-reliability versions are available.

The high-performance DSP24 array-processor chip and its associated intellectual-property cores for signal and image processing in the frequency domain target applications that perform operations on large arrays of data. It is a pass-based processor, with each function valid for one complete pass. Each operation code defines a basic flow for the desired operation that repeats for multiple pairs of data to complete one pass. For typical array-processing applications, such as FFTs, the device sets up a function code (for example, BFLY32). Radix32 butterfly then clocks the whole data array into the DSP24 and applies the function to the whole array. A latency occurs when you implement the DSP24 functions, for which the MMU24 automatically compensates when you use it in a system. The pipelined systolic structure allows you to cascade multiple DSP24s for increased performance and higher radices. This structure permits high-speed operation on an unlimited array size with support for enhanced read-only FFT, double-length FFT, dual FFT, and stacked FFT to reduce latency.

Addressing and processing modes: The DSP24 addressing includes digit reversing, read-only-FFT addressing, fast sine/cosine, decimation, interpolation, modulo increment/decrement, array padding, zero filling, radix2 through radix1024 patterns, and parameterized user sequences.

Special instructions or integral-peripheral functions: The DSP24 includes radix2 through radix1024 instructions, FIRs, and matrix multiplies. It can perform no-overhead window functions and filter/image multiplies and uses five bidirectional data ports for any-port-to-any-port data routing.

Development support: The DSP24 and optional MMU24 software-development kit come with C models and optional VHDL models. DSP Architectures offers the DSP24-EVM evaluation module. Valley Technologies (www.valleytech.com) offers board and module products, including the VectorWare language.

EQUATOR TECHNOLOGIES BSP-15 and MAP-CA

at a glance:

• Processor enables multiformat, high-definition decoding.

• Audio/video encoding/decoding engines support the processor.

The BSP-15 processor, a four-issue, superpipelined VLIW (very-long-instruction-word) architecture, includes four integer ALUs, two 64-bit SIMD ALUs, and two 128-bit SIMD (single-instruction-multiple-data) ALUs. The processor has 32 1-bit predicate registers, eight 128-bit registers, and 128 32-bit registers, which it can pair into 64-bit registers. The BSP-15 processor family targets video- and image-processing applications and is backward-compatible with Equator’s MAP-CA chips. The BSP-15 supports as many as 50 billion operations/sec, 8 billion MACs/sec, 16 billion SAD (sum of absolute differences)/sec, and as many as six MPEG-2 D1 decodes.

The Equator MAP-CA BSP (broadband-signal-processor) chip is 100% programmable in C and targets consumer applications. The VLIW core includes four execution units on two clusters for VLIW parallel processing at the instruction level, native SIMD operations, four-way-set- associative, nonblocking write-back data cache, and a two-way- set-associative instruction cache. The MAP-CA chip can perform 30 billion operations per second while running common media-processing tasks, such as motion estimation. Equator designed the MAP-CA processor to operate at a core voltage of 1.8V with I/O signals of 3.3V. Depending on processor speed and application, the MAP-CA processor dissipates 2.5 to 6W of power. The MAP-CA processor is available in a 352-pin BGA package.

The processor stores instructions in a compressed format and presents them to the VLIW processor via a 32-kbyte, two-way set-associative instruction cache with an LRU (least recently used)-replacement policy. It presents data to the processor by a 32-kbyte, four-way set-associative, four-bank-interleaved data cache using an LRU-replacement policy. Separate instruction, data, and DMA MMUs, each with a fully set-associative, 16-entry TLBs (translation look-aside buffers), provide memory protection. Off-chip memory connects via a glueless 64-bit SDRAM/SGRAM interface supporting as much as 128 Mbytes of external memory. The BSP processor family is 100% C/C++ programmable, allowing designers to port new and evolving video-compression algorithms to the BSP-15 processor platform, using Equator’s optimizing compilers. A single BSP-15 chip can replace multiple fixed-function devices, such as hardwired-MPEG chips.

The variable-length encoder/decoder coprocessor with 4-kbyte instruction and 4-kbyte data memories offloads bit-serial tasks from the VLIW core and handles variable-length encoding and decoding. The video-filter coprocessor, aided by a 6-kbyte line buffer, provides as many as four vertical-tap and five horizontal-tap filters. The DataStreamer, a programmable, 64-channel DMA controller with 8 kbytes of buffering, provides high data throughput. The display-refresh controller provides color-space conversion, palette-table look-up, and hardware-cursor functions. A DES coprocessor accelerates DES encryption and decryption.

Special instructions or integral-peripheral functions: Specialized video instructions provide video acceleration, and specialized audio instructions enable efficient mapping. The programmable format, 64/32-bit SDRAM controller requires no additional glue logic. The PCI bus is compatible with 3.3V, 33/66-MHz, 32-bit, PCI Revision 2.2 and includes an internal host arbitrator. Integrated peripheral interfaces include a IIC (inter-IC) serial-I/O-bus-control port, flash-ROM controller, S/PDIF (IEC958) and IIS serial-audio I/O ports, an 8-bit ITU-T BT.656 video-encoder-output port, and control signals for an external-video VCXO timing-control loop for MPEG transport-clock recovery. The programmable SVGA-display refresh controller provides 24-bit (8 bits times three), 135-MHz digital-to-analog conversion. The device also includes two multipurpose ports, each of which can function as an ITU-R BT.656 video-decoder-input port or a transport-channel-interface port.

Development support: Version 6.0 of Equator’s iMMediaTools software-development tool kit allows designers to develop and deploy videocentric applications with the BSP-15 chip running Linux. Equator and its software partners offer a range of video and codecs, including MPEG-2, MPEG-4, H.263, H.264, MJPEG, Windows Media 9 Series, RealVideo9, DivX, MP3, AC3, AAC, and other proprietary, low-bit-rate, streaming-video codecs. They also offer reference designs for digital-security and surveillance applications, including digital-video-recorder, IP-camera, motion-detection, motion-tracking, biometrics, and camera-steadying applications.

The Tetra hardware platform supports rapid prototyping with a BSP processor targeting IP smart cameras, digital-video recorders, or IP-based Internet streaming-video applications. The modular design includes the Tetra CPU board, an open peripheral interface for add-on modules, and add-on “personality” modules. The Tetra CPU board measures 2.75×4 in., supporting hardware-reference designs for small-footprint applications.

The broadband video-on-demand reference platform, for low-bit-rate video-on-demand systems with Internet access and content security, provides less than 1 mbps with DVD-quality video. The multiformat, high-definition DVD player/recorder reference design can support popular film, Internet, and DVD-video formats, including Microsoft Windows Media 9 Series, encoding and decoding at standard and high definition.

EVATRONIX C32025TX

at a glance:

• The C32025TX architecture is four times faster than the original architecture at the same clock speed.

• Most instructions support repeat mode.

The C32025TX, a three-stage-pipelined, 16-bit, fixed-point DSP core, implements the same instruction set as Texas Instruments’ TMS32025 and provides the same interrupts, serial interface, and timer and executes most of instructions in a single clock time. The C32025TX is a microcode-free design targeting ASIC and FPGA implementations that avoids internal tristates and is strictly synchronous with both-edge clocking and synchronous reset. The C32025TX implements a Harvard-type architecture, maintaining two separate program- and data buses for full-speed execution. The program bus carries instructions and immediate operands; the data bus interconnects various components and carries data between any data- memory space. Both buses can carry data for single-clock MAC operations.

Addressing and processing modes: The C32025TX supports memory-direct, indirect, and immediate addressing modes. Direct mode uses a 9-bit page pointer and the seven least significant bits of the instruction word. Indirect mode and operations with reversed-carry propagation use 8×16-bit registers and a 16-bit auxiliary-register arithmetic unit. Immediate addressing mode uses a 16-bit-long-instruction immediately following the instruction word.

Special instructions or integral-peripheral functions: The instruction set and control signals support block memory transfers, communication to slower off-chip devices, and multiprocessing implementations. Most instructions support repeat mode for block moves, MAC (multiply-accumulates) operations, I/O transfers, and table reads and writes. The C32025TX includes single-clock MAC instructions, two large on-chip RAM blocks, eight auxiliary registers with dedicated arithmetic unit, a serial interface, and a hardware timer. The C32025TX has a 16-bit reload timer and a synchronous serial port for a direct codec interface.

EVATRONIX C56000

at a glance:

• Core delivers 80 MIPS when you implement it in a 0.18-micron process (160 MHz).

• Two parallel moves are possible in one instruction cycle.

The C56000 is a three-stage-pipelined, 24-bit, fixed-point DSP core. The efficient modified-Harvard architecture provides high precision and performance using independent X/Y-memory accesses. The C56000 implements the same instruction set and provides the same peripherals and interrupts as the industry-standard DSP56002. The architecture maximizes processing power by maintaining separate two-data and one-program buses for full-speed execution. Two clock-cycle arithmetical instructions, three on-chip RAM blocks, an address-generation unit with 24 dedicated registers, two full-duplex serial interfaces, a hardware timer, and a host interface make the processor appropriate for data-intensive signal processing. The address-generation unit, program-control unit, ALU; memory; and peripheral block operate independently of and in parallel with the other units using a sophisticated bus system. Instruction prefetch, 24×24-bit multiplication, 56-bit addition, two data moves, and two address-pointer updates can execute in one instruction cycle.

Addressing and processing modes: The C56000 DSP has eight sets of three 16-bit registers: address, offset, and modifier. It supports direct, indirect, and immediate addressing modes and has varied indirect-addressing modes using linear, modulo, and reverse-carry arithmetic. It executes two 16-bit address calculations every instruction cycle for the program and X/Y data-memory spaces.

Special instructions or integral-peripheral functions: Most arithmetic instructions of C56000 use parallel moves. The core supports nested loops and can repeat one instruction or a block of instructions a set number of times. It performs single-cycle MAC (multiply-accumulate) instructions with rounding. The SCI and SSI ports support direct codec interfacing, and 24 general-purpose-I/O pins, in parallel with the 24-bit timer, enable the DSP to work as a microcontroller.

Development support: These DSP cores are compatible with instruction-set architectures of once widely used chips, which Texas Instruments and Motorola made obsolete; therefore, designers may develop software for these cores with any compiler and assembler that generate code for those architectures. Some cores include First Silicon Systems’ (www.fs2.com) on-chip instrumentation. The on-chip-debugging-support module, a JTAG-accessible plug-in, can control the processor (modify any register, execute any instruction and run it in step mode) and set breakpoints on any instruction or data. Signum Systems’ (www.signum.com) in-circuit emulator supports debugging as fast as 100 MHz for the R80515 and features real trace mode and real-time visibility into the memory and registers.

HITACHI SEMICONDUCTOR SH-DSP AND SH3-DSP

at a glance:

• The SH7622 can perform 130 MIPS at 100 MHz.

• The SH7727 can perform 208 MIPS at 160 MHz.

Processors in the SH-DSP series (SH7616, SH7622, and SH7065) combine a 32-bit RISC CPU and a 16-bit integer DSP unit into a single core. The DSP unit can execute single-cycle, 16×16-integer multiplies and multitask its operations. Hitachi’s SH7616 is a CMOS single-chip microcontroller that integrates a 10/100-Mbps Ethernet controller supported by two 2-kbyte FIFOs and a multichannel DMA controller targeting Ethernet applications, such as network video/printers, network terminals, and management processors. The SH7065 integrates 256 kbytes of on-chip flash.

Processors in the SH3-DSP series (SH7727, SH7729R) combine a 32-bit RISC CPU and 16-bit integer DSP unit into a multitasking core with a four-bus structure targeting Web/Smartphone, handheld-PC, Internet-terminal/IP-fax, digital-still- camera, and security-terminal applications. SH3-DSP devices include 16 kbytes of X/Y RAM, 16-kbytes of cache (ways 2 and 3 lockable), a bus-state controller for glueless connection to SDRAM, and on-chip JTAG and real-time instruction-trace-debugging modules. The SH7729R includes data protection and virtual memory.

Addressing modes: These devices support direct- and indirect-register, predecrement or postincrement indirect-register, indirect-register-with-displacement, indirect-indexed-register, indirect-global-base-register-with-displacement, indirect-indexed-global-base-register, indirect-program-counter-with-displacement, and program-counter-relative immediate addressing.

Special instructions or integral-peripheral functions: The SHDSP and SH3-DSP use a 16- and 32-bit instruction set that supports one-cycle multiplication/addition, operand-unrelated parallel moves, conditional execution for DSP datapath instructions, multiprecision arithmetic in microcontroller instructions, and single-cycle exponent detection. (DSP operations are all 32-bit instructions.)

The SH7622 SH-DSP core device includes high-speed on-chip USB. SH3-DSP devices include a memory-management unit, a timer, a real-time clock, an interrupt controller, and a serial-communication interface. The SH7727 includes USB host and LCD controllers that support bus-master functions. The SH7729R includes infrared communication, an ADC, a DAC, and power management.

Support: Hitachi and third parties offer evaluation kits, emulators, companion chips, reference-design platforms, software board support, RTOSs, middleware, and application packages. Hitachi offers middleware for the SH-DSP and SH3-DSP covering telephony applications, including G.729, G.725, and G.723.

HYPERSTONE E1-16XSR AND E1-32XSR

at a glance:

• A single-core RISC/DSP suits battery-driven multimedia devices.

• Core gate count is 35,000 without RAM.

Hyperstone E1-32XSR is a single-core RISC/DSP targeting digital-still-camera applications. All of the instructions, including the DSP instructions, use RISC principles. Parallelism exists between the ALU, the DSP, and the load/store units. Hyperstone implements the core as a static design, and it can operate as fast as 220 MHz with a current consumption of 40 mA. The architecture includes SDRAM, EDO RAM, flash memory, I/O-bus interfaces, on-chip PLL, 16 kbytes of SRAM, and a timer. Variations are available on request. The bus interface provides four external memory areas, each 1 Gbyte in size with individual bus width and bus timing. You can control the on-chip PLL via software, making possible a speed variation by a factor of as much as 16 within one clock cycle.

Addressing and processing modes: The core bases all instructions on the load/store principle that RISC processors use. It supports subword processing, a kind of “lean VLIW (very-long-instruction-word)” principle.

Development support: Windows-and Linux-based system-development tools are available. Embedded Linux is the supported operating system. A network of partners offers services and capabilities, including ASIC design and Bluetooth IP.

IMPROV SYSTEMS JAZZ

at a glance:

• Direct on-chip data memories handle processor-to-processor data communication.

• All processors attach to a single Q-Bus that enables queuing of tasks.

The Jazz DSP configurable, VLIW (very-long-instruction-word) architecture incorporates overlaid datapaths, a distributed register system, code compression, and power management. The architecture allows designers to customize the computational resources and instruction set of the processor. Designers can customize the Jazz PSA (programmable-system architecture) to optimize key application algorithms. The Jazz PSA defines a processing platform comprising multiple Jazz processors, nonvolatile instruction memory, configurable I/O interfaces, and hardware support for u-tasking. The DSP-core architecture facilitates rapid design modifications without compromising the verification integrity and tool chain of the processor. The Jazz PSA can scale from a single Jazz DSP core to a system-level platform implementation that many unique processors in an interconnect structure. The orthogonal memory structure enables the device to independently map, address, and configure the instruction and data-memory spaces for width and size.

Addressing and processing modes: Supported standard addressing modes include direct, indirect, indexed, immediate, displacement, bit reverse, bit-reverse index, vector index, and postincrement. A wrap mode supports circular buffers.

Special instructions or integral-peripheral functions: Special instructions support single-cycle built-in library functions for common signal-processing data transforms, and a set of task control instructions supports the unique u-task scheduling in the PSA.

Development support: The Jazz DSP supports a flexible design methodology that customizes the computational resources and instruction set of the processor. The development-tool chain includes an IDE, a compiler, an assembler, an instruction-set simulator, a profiler, a debugger, and FPGA-emulation support. The Jazz PSA Composer tool suite supports processor customization in a graphical design environment. The Jazz PSA standard tool suite supports programming for unique processor configurations so that designers do not need custom programming tools.

Improv’s Rehearsal boards provide a near-real-time system for designers to run configurations of the Jazz PSA core and to verify that designer-defined DSPs run with other elements of the overall system. Improv offers platform solution kits that are a collection of hardware and software components, such as custom Jazz DSPs, application software, and reference designs, targeting application-oriented SOC (system-on-chip) development. Acappella is a family of application-optimized hardware and software targeting voice-over-packet applications. To better meet the needs of resource-constrained designs, Easy Jazz kits offer suites of application software, hardware-integration blocks, and verification code.

LSI LOGIC ZSP400, LSI402ZX, AND LSI403LP

at a glance:

• Dual add-compare-select operations in one cycle support efficient Viterbi decoding.

The ZSP400, a dual-MAC (multiply-accumulate) unit, four-issue superscalar processor architecture, uses a 16-bit instruction set with dual 16-bit arithmetic operations that you can combine to provide a high-precision, 32×32-bit single-cycle multiply and add to support high-resolution audio and multimedia applications. The ZSP400 implements a five-stage, four-way superscalar pipeline to process as many as 20 instructions at a time. The processor’s execution unit contains two ALUs.

The LSI402ZX is a high-performance, 16-bit, fixed-point DSP core targeting voice-over-network CPE/IAD (customer- premises-equipment/integrated-access-device) devices, infrastructure, wireless-infrastructure, and audio applications. The LSI402ZX includes 62k words of instruction RAM and 62k words of data RAM. The LSI403LP is a low-power, 16-bit, fixed-point DSP core targeting voice-over-network CPE/IAD devices and audio applications. The LSI403LP provides 16k words of instruction RAM, 16k words of data RAM, and 16k words of instruction- or data-configurable memory. An eight-channel DMA controller, which transfers instructions or data to and from memory, supports both devices.

Addressing and processing modes: The ZSP400 provides two independently enabled circular buffers and supports reverse-carry addressing. Reverse-carry addressing is an alternative mode of indexing the base-address registers that speeds FFT and similar operations that require modification of the next-load or -store address in a reverse-carry fashion.

Special instructions or integral-peripheral functions: The ZSP400 can perform a single-cycle add-compare-select for efficient Viterbi decoding. It also supports bit manipulation, 32-bit arithmetic, logic operations, and two-cycle complex-multiply instructions. The LSI402ZX and LSI403LP include two high-speed TDM serial ports, an 8-bit (LSI403LP) or 16-bit (LSI402ZX) host-interface port, an external memory-interface unit, a four-pin (LSI403LP) or an eight-pin (LSI402ZX) programmable I/O port, and an IEEE 1149.1 JTAG port for program downloading and debugging.

LSI LOGIC ZSP500

at a glance:

• Power-management controls dynamically switch execution units on or off based upon program usage.

• Designers can extend the instruction set by as many as 256 customer instructions.

The ZSP500, a low-power, high-performance, dual-MAC (multiply-accumulate) unit, quad-issue superscalar processor architecture, has an instruction set rich with DSP capabilities. The ZSP500 uses a 16- and 32-bit instruction set with dual 16-bit arithmetic operations that you can combine to provide a high-precision, 32×32-bit, single-cycle multiply and add supporting high-resolution audio and multimedia applications. The ZSP500 implements an eight-stage, four-way-superscalar pipeline to process as many as 32 instructions at a time. The processor’s execution unit contains two MAC units, two general-purpose ALUs and two dedicated ALUs for address generation. The LSI500P is a silicon prototyping vehicle that incorporates the ZSP500 core, the memory subsystem, 256k words of SRAM, and an integrated AMBA/AHB interface with the AMBA I/O pins available off-chip as well as complete pin access to the coprocessor port.

Addressing and processing modes: The ZSP500 provides for both Harvard and unified memory-addressing schemes. The ZSP500 supports a range of indexed and bit-reversal addressing. Reverse-carry addressing is an alternative mode of indexing the base-address registers that speed FFT and similar operations that require modification of the next-load or -store address in a reverse-carry fashion.

Special instructions or integral-peripheral functions: The ZSP500 includes a coprocessor interface that allows designers to add as many as 256 tightly coupled custom instructions to the processor without affecting the processor baseline datapaths. The ZSP500 core includes a memory subsystem that is configurable for data- and instruction-memory sizes from 4k to 128k words per block. The ZSP500 comes with an ARM ABMA/AHB interface bridge and a reference system with sample AMBA/AHB peripherals.

LSI LOGIC ZSP600

at a glance:

• Three add-compare-select operations in one cycle support efficient Viterbi decoding.

• Designers can extend the instruction set by as many as 256 customer instructions.

The ZSP600, a high-performance, quad-MAC (multiply-accumulate)-unit, six-issue superscalar processor architecture, uses a 16- and 32-bit instruction set with dual 16-bit arithmetic operations. You can combine these operations to provide a dual, high-precision, 32×32-bit single-cycle multiply and add that is necessary for high-resolution audio and multimedia applications. The ZSP600 implements an eight-stage, six-way-superscalar pipeline to process as many as 48 instructions at a time. The processor’s execution unit contains four MAC units, four general-purpose ALUs, and two ALUs dedicated to address generation. The ZSP600 features dual independent 64-bit load/store ports, providing as much as 6.4 Gbytes/sec of I/O.

Addressing and processing modes: The ZSP600 provides for both Harvard and unified memory-addressing schemes. The ZSP600 supports a wide range of indexed and bit-reversal addressing support. Reverse-carry addressing is an alternative mode of indexing the base-address registers that speed FFT and similar operations that require modification of the next-load or next-store address in a reverse-carry fashion.

Special instructions or integral-peripheral functions: The ZSP600 includes a coprocessor interface that allows designers to add as many as 256 tightly coupled custom instructions to the processor without affecting the processor baseline datapaths. The ZSP600 core comes with a memory subsystem that is configurable for data and instruction memory, from 4k to 128k words per block. The ZSP600 comes with an ARM ABMA/AHB interface bridge and a reference system with sample AMBA/AHB peripherals.

Development support: LSI delivers all three licensable core-product offerings in a technology-transfer package that includes Verilog RTL source code; scripts for Design Compiler, Physical Compiler, or both, as well as static-timing-analysis scripts for Primetime; and a verification suite to test implementations for correct construction, as well as an example system to provide an out-of-the-box system as a reference. Designers can tune these scripts to vary the gate count, die size, clock speed, and power dissipation of all three core offerings for tailoring to an application’s requirements. These core-product technologies incorporate AMBA interfaces to allow a glueless interface to ARM-based microprocessor designs. The ZSP500 and ZSP600 have extended debugging support to include on-core profiling, ETM (Embedded Trace Module), and real-time hardware trace. Each core includes documentation, such as the ZSP Architecture for Programmers, the Core User’s Guide for system designers, and a VLSI Implementation Guide for chip designers.

LSI provides an integrated ZSP software-development kit that supports all three processor cores and includes an optimizing C compiler, an assembly optimizer, a linker, an assembler, cycle- and instruction-accurate simulators, and a debugger with advanced features, such as a pipeline viewer and instruction-grouping analyzer. The software-development kit incorporates a library of commonly used DSP-function calls and supports development on both Windows and SPARC Solaris platforms. The cycle-accurate simulator can serve as a DLL to link to larger simulation-model environments, and designers can add their own models for custom peripherals. LSI Logic has combined the cycle-accurate simulator with a bus-interface model to provide a mixed-mode simulation capability in VCS/ModelTech environments.

Corelis (www.corelis.com), Macraigor Systems (www.macraigor.com), and Green Hills Software (www.ghs.com) offer a variety of JTAG probes. Third-party modeling support of the ZSP includes a kit for Cadence’s (www.cadence.com) Signal Processing Workstation on the ZSP400 and a processor-support kit for Mentor Graphic’s (www.mentor.com) Seamless co-verification tools for all three DSP cores. Green Hills Software offers the Multi software-development tool chain, which includes an optimizing C compiler, an assembler, a linker, a cycle-accurate simulator, a debugger suite, and additional features for project building and code balancing. It can interface with Matlab for data visualization and multicore debugging in a heterogeneous processor environment that can include ZSP, ARM, MIPS, and PowerPC processors. The multiprocessor core-debugger support operates from a single JTAG interconnection, supporting low-pin-count interfaces for SOC (system-on-chip) designs.

LSI offers royalty-free source-code licenses of production- grade, assembly-optimized ZSP application software for audio, multimedia, and wireless markets. These modules comply with LSI Logic’s open-architecture ZOpen Software Framework, a royalty-free, C-source-code product that provides integration guidelines, supporting utilities and a methodology that standardizes application development. ZSP software-application partners provide ZOpen-compliant algorithms. Optional real-time operating systems are available, including those from OSE Systems (www.ose.com); Micrium U-COS (www.micrium.com); and Express Logic (www.expresslogic.com), which provides Thread-X support for ZSP cores.

Click here for devices M through Z.

Click here for devices M through Z.