Design kit boasts four 3.125-Gbps links
By Gabe Moretti -- EDN, September 5, 2002
Xilinx derived the RocketIO design kit for Cadence (www.cadence.com) SpecctraQuest from the Rocket I/O design kit that Teradyne (www.teradyne.com) develops and markets. A key component of the design kit, the XAUI (10-Gbps attachment-unit interface)-compliant backplane for FPGAs, provides connectivity at 10-Gbps data rates and includes four 3.125-Gbps links. The product also includes single-pair coupled connector models for Teradyne's VHDM-HSDTM connectors to provide a serial backplane operating as fast as 3.125 Gbps on one channel. The high-speed, serial signaling approach is compatible not only with backplanes, such as XAUI and Xilinx's Aurora, but also with connectivity standards, such as PCI-Express (3GIO), InfiniBand, and PICMG.
Xilinx has also released a Virtex-specific rules deck for Atrenta's (www.atrenta.com) Spyglass analysis product. The first release of the Virtex predictive-analysis product comprises an extensive set of rules that analyze a design for good FPGA-design practices. These design practices include ensuring that all inferred registers use synchronous resets, ensuring that finite-state machines are coded into separate processes, detecting combinational feedback loops, and checking that multiple clocks are not part of the same block or process statement. Atrenta sells and supports Spyglass 3.1, which includes the Xilinx-specific rule set for no extra charge. It runs on Sun/Solaris, HP-UX, and RedHat Linux.
Xilinx, 1-408-559-7778, www.xilinx.com.
