RAM-transformed logic builds on a no-batteries foundation
By Brian Dipert -- EDN, July 25, 2002
An increasing percentage of the programmable-logic industry's players are turning to SRAM-based process technologies to build their latest products (see "Lithography advancements 'axcelerate' antifuse lineage," EDN, July 11, 2002, pg 22). In FPGAs, this trend has historical underpinnings: Aside from a brief antifuse experiment, market leader Xilinx (www.xilinx.com) has always built its chips on SRAM processes, and No. 2, Altera (www.altera.com), has exclusively relied on SRAM for successive generations of its Acex, Apex, Flex, Mercury, newest Stratix, and ARM-inclusive Excalibur parts.
Lattice Semiconductor, fresh from its acquisition of Agere Systems' Orca FPGA product line, represents the latest trend-follower, rolling out two SRAM-based architectures—one FPGA and the other, surprisingly, CPLD. Both product families include not only the power-dependent logic and routing configuration cells and memory blocks, but also the nonvolatile-EEPROM configuration-storage arrays on one die. The chips autoconfigure on power-up within a few hundred microseconds; you can subsequently reconfigure both the volatile and the nonvolatile memory locations through serial IEEE 1532 and parallel system-configuration interfaces, and no insecure external bit stream is available that design thieves can tap into (see "Cunning circuits confound crooks," EDN, Oct 12, 2000, pg 103).
Aside from its volatile-plus-nonvolatile-memory amalgamation, Lattice's ispXPGA is in many other respects a conventional modern FPGA. Each programmable function unit contains four synthesis-friendly, four-input look-up tables, which can alternatively implement a 64-bit single port or a 32-bit dual-port distributed-memory block; eight registers; dedicated hardware to implement counters, multiplexers, adders, and conventional and Booth multipliers; and input and output switch matrices. Discrete block RAMs, configurable as either 512×9 or 25×18 bits, support FIFO and single- and dual-port-memory structures with 3-nsec access times and both width- and depth-cascading capability.
Each ispXPGA programmable-I/O structure, residing between the programmable function units and the I/O buffers, contains input, output, and output-enable registers and offers configurable output slew rate and input delay; this delay enables a zero-hold-time configuration. PLLs and associated 850-Mbps serializer/deserializer circuits, along with built-in 10B/12B support, form the heart of the chips' high-speed serial interfaces, but you have to implement 8B/10B encoding and decoding in general-purpose logic. All devices, regardless of logic and memory density, include eight additional generic system-clock PLLs.
Lattice's ispXPLD architecture is the less conventional of the company's two latest unveilings (Picture). Philips' CoolRunner XPLA2, which acquiring company Xilinx promptly relegated to end-of-life status, and Cypress Semiconductor's Quantum38K and Delta39K devices are the only other examples so far of SRAM-based CPLDs. Each ispXPLD multifunction block, when in product-term mode, is reminiscent of Lattice's SuperWide ispLSI5000 devices with 68 inputs and 32 macrocells. Alternatively, the multifunction block can construct an 8-kbit dual-port RAM, 16-kbit single-port or pseudo (one read/write port, one read-only port) dual-port RAM, 16-kbit FIFO with built-in control logic, or 128×48-bit ternary content-addressable memory. Because you can preload all of the memory structures at power-up, you can alternatively use them as ROMs.
One of the four ispXPLD I/O banks does double duty as the system-configuration port, and each device, independently of logic and memory density, includes two system-clock PLLs. IspXPLD chips, like their ispXPGA counterparts, run at 1.8, 2.5, or 3.3V with no speed penalty at lower voltages, according to the manufacturer. The $350 (1000) is XPLA1200 comes in a 900-bump fine-pitch BGA, and the $17.75 (1000) ispXPLD5512MC comes in a 256-bump fine-pitch BGA. Both devices are available for sampling now and will enter production in the third quarter; the ispXPLD5512MC is available for sampling, and production is scheduled for late in the third quarter (Table 1 and Table 2). Lattice's ispLever development software now supports both product families, and intellectual-property-core and third-party-software support is in progress.
Lattice Semiconductor, 1-503-268-8000, www.latticesemi.com.
