Analog/digital hybrid supervises supplies
By Brian Dipert -- EDN, January 23, 2003
Lattice Semiconductor's PowerPac devices blend the programmable-digital-logic core of the company's PLDs with the programmable-analog capability of the vendor's ispPAC devices.
Designed to monitor and sequence the supply voltages for advanced, complex ICs and systems, the $9.95 (10,000) PowerPAC1208 combines several key functions in a single chip (Picture). These functions include a 250-kHz oscillator and four timers; four noise-tolerant digital-signal inputs; 12 programmable threshold comparators; a 16-macrocell PLD; four programmable, high-voltage FET drivers; and four open-drain digital outputs. The chip operates across a 2.25 to 5.5V range and comes in a 44-pin TQFP.
The timers for watchdog, delay, and other functions measure 32-µsec to 512-msec delays, and the comparators specify a 1% step size and 192 steps, claimed better-than-1.2% accuracy, a programmable glitch filter, and an on-chip precision reference. The ispMach4000-derived logic block includes 32 inputs and outputs and supports as many as 80 product terms. The FET drivers output 0.5 to 50 µA in 32 steps and 8 to 12V in eight steps and offer programmable ramp rates and an open-drain option.
The PowerPAC1208 and companion free PAC-Designer 1.9 design software are available for sampling and are scheduled to go into full production by the end of the first half of the year. The $149 PACsystemPOWR1208 evaluation kit contains a development board and configuration-downloading cable. Also in the first half of the year, Lattice Semiconductor plans to ship first samples of its pin-compatible, lower cost PowerPAC604, which has half the number of inputs and outputs, lacks FET drivers, and includes half the programmable-logic density.
Lattice Semiconductor, 1-503-268-8000, www.latticesemi.com.
