FPGA takes a clean-slate approach to low prices
By Brian Dipert -- EDN, October 17, 2002
I engage in an almost-daily mindset tug of war with the semiconductor vendors I cover. They all want to tell me about their latest and greatest high-end architectures, tailored for a few high-volume customers. I remind them that those customers represent a small percentage of my readers and that most of you are content with more mainstream—read: less expensive—architectures. Their responses, in the form of products such as Altera's Acex and Xilinx's (www.xilinx.com) Spartan families, often follow what I like to call the Celeron approach to cost savings, a term familiar to those of you who follow PC-processor trends.
Take an Altera Apex or a Xilinx Virtex chip (see "Third annual programmable-logic directory," EDN, Sept 5, 2002, pg 44). Removing mention in the documentation and support in the design software for esoteric features and a portion of the embedded memory (though both likely still reside on the die) reduces test time and boosts yields. Putting the chip only in low-cost packaging reduces the number of line items that the manufacturer must support. Don't push the speed or the power-consumption specifications or use an exotic variant of the manufacturing process to build the chips, again to maximize yield and minimize cost.
Voilà: a price-focused product line requiring little development time. But the cost savings are limited, especially if the vendor never performs a redesign that removes the now-unspecified features. Alternatively, the supplier can build a new architecture from the foundation up with economy in mind. It might take longer for resultant devices to move from the drawing board to the production line, but the potential cost savings are more significant. Altera, with Cyclone (Picture), has chosen this path in a more extensive continuation of the approach the company took with Flex 6000, which it introduced in 1997. Altera's focus with Cyclone is on lower densities, lower speeds, and a more restricted set of features than that of the high-end Stratix family. This focus means that Cyclone contains only short global routing lines—a shift from the company's long-line past. Altera builds Cyclone on a detuned and one-metal-layer-reduced variant of Stratix's 0.13-micron copper process, at foundry partner TSMC (www.tsmc.com).
The Cyclone logic-cell structure appears to synthesis tools similar to the cell of other Altera FPGAs. But internal optimizations have made it 30% smaller than the Stratix logic cell. Cyclone comes with a lower memory-to-logic ratio than Stratix, the embedded memory runs at lower speeds (estimated at 200 MHz maximum), and Altera has removed support for dedicated FIFO circuitry, full dual-port capability without density trade-offs, and other specialty-memory features. Cyclone FPGAs come with a maximum of two PLLs, which lack spread-spectrum capability, have limited system-management features, and run at lower-than-Stratix-compatible top speeds but offer additional multimedia-focused capabilities at lower speeds. The I/O buffers focus on single-ended protocols, such as 66-MHz PCI, and don't include Stratix's integrated termination resistors, though they do comprehend some differential-signaling schemes at speeds as high as 311 Mbps. The I/O buffers also contain dedicated FCRAM (fast-cycle RAM) and DDR (double-data-rate) SDRAM circuits and support programmable slew rate and drive strength.
At first glance, Altera seems to have stripped out a lot of capabilities during the 15 months it will take to bring Cyclone from concept to production. But look at the resultant prices (Table 1), which Altera estimates to be less than half the published prices of even the most aggressive competitor and which reflect an average 60% smaller die than that of a similar-logic-density Stratix device. For example, a full-featured Nios CPU soft core takes up only half of the cheapest ($4) Cyclone family member. Does anyone want a $2, 32-bit RISC CPU? I thought so. Altera is also offering a companion suite of discrete configuration memories for $1 to $3; design-software support is now available. Simulations show Cyclone-based designs running on average much faster than earlier generation Acex 1K counterparts, and first chip samples will be available for sampling in early January. Until then, if necessary, you can develop prototypes with Stratix parts, keeping in mind the differences in features between the two families.
Altera, 1-408-544-6879, www.altera.com.
