Hybrid-gate-array technology promises shorter cycle time and lower NRE and unit costs
By Bill Schweber -- EDN, January 24, 2002
Targeting FPGA-to-ASIC conversions and first-time ASIC designs, a 0.18-micron, hybrid-process gate array from AMI Semiconductor hits a triple play of cutting cycle time, slashing up-front NRE costs, and yielding higher chip-device usage for lower part cost and lower break-even point for conversion decisions. The 1.8V XPressArray platform is also a drop-in replacement for converting Xilinx (www.xilinx.com) Virtex-E and Altera (www.altera.com) Apex-E FPGAs to lower cost ASICs (Picture).
The new system uses a hybrid manufacturing process to achieve these goals. TSMC (www.tsmc.com) performs the wafer front-end processing for AMI in a standard, high-volume, low-cost process, and AMI performs final packaging and back-end metallization to finish the design to meet customer requirements.
AMI's technology supports system clocks as fast as 250 MHz and local clock speeds as high as 350 MHz, along with device densities of as many as 2.6 million gates, as many as 200 million internal registers, and 31 kbits to 1.4 Mbits of configurable and initializable memory. You can choose I/O from a wide menu of standards, such as low-voltage TTL, CMOS, and PECL and 622-Mbps LVDS, and the devices are compatible with 1.8V through 5V I/O schemes. Clock-management circuitry modules have as many as 12 digital delay-lock loops and four PLLs. AMI also includes embedded scan-test logic for a high level of fault-coverage testing.
Without design software and tools, this new technology approach would be nice but useless. No problem: AMI offers FPGA-to-ASIC-conversion tools, plus synthesis libraries for commercial synthesizers, such as Synplicity (www.synplicity.com) Synplify ASIC and Synopsys (www.synopsys.com) Design Compiler. You can also use the AMI RTL handoff-flow tool to submit RTL descriptions, scripts, and timing constraints; the company then checks, synthesizes, lays out, and verifies timing closure of the design.
Although the cost for such products is hard to assess without a design example, AMI claims that the NRE charge and post-NRE production costs for the XPress-Array are as much as 70% lower than those for cell-based or standard-cell ASIC designs, which typically cost $400,000 to $500,000.
AMI Semiconductor Inc, 1-208-233-4690, www.amis.com.
