FEC processor targets metropolitan-area networks
By Nicholas Cravotta -- EDN, January 9, 2003
The 10-Gbps MTC6134 digital-wrapper processor from Multilink Technology supports EFEC (enhanced forward-error correction). This device features a full SONET/SDH section and line-overhead processing, 10-Gbps-Ethernet performance monitoring, and G.709 digital-wrapper termination and generation. It also provides 8.5 dB of net coding gain at 1×10–15 corrected bit-error rate with 7% overhead and consumes 3.5W using an optional proprietary FEC. Standard block-oriented Reed-Solomon code RS(255,239) is also available using the same 7% overhead. Available now, the MTC6134 comes in an 896-pin, 35×35-mm CBGA package, and sample price is $750 (one).
Multilink Technology, www.mltc.com.
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