Software makes full use of 8051's interrupt system
Edited by Bill Travis
Deng Yong, Shanghai Jiaotong University, China -- EDN, December 6, 2001
The program in Listing 1 uses a pseudo-RETI instruction to provide a five-priority-level interrupt system for the 8051P microcontroller. The interrupt-priority order, from high to low, is INT0 IT0 INT1 IT1 INTP. Before the pseudo-RETI instruction arrives in the IT0 or IT1 interrupt-service routine, the address of the first instruction, which is after the pseudo-RETI instruction, goes back into the stack. The internal, nonaddressable flip-flop associated with IT0 or IT1 clears to acknowledge a higher interrupt after execution of the pseudo-RETI instruction, while the IT0 or IT1 interrupt-service routine executes continuously until the RETI instruction arrives. Hardware circuits can exchange the INT1 and INT2 interrupts, and software can set the IT1 and IT2 interrupts.
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