Flash upgrade requires control revisions
By Brian Dipert -- EDN, September 19, 2002
Toshiba follows up last November's introduction of a 1-Gbit MLC (multilevel-cell) NAND flash memory, containing 0.5 Gbit of storage locations, with a conventional SLC (single-level-cell), 1-Gbit memory built on a 0.13-micron process. The company has made other modifications to the earlier architecture, such as increasing the size of dual embedded read- and write-page buffers to 2112 bytes and boosting the erase-block size to 135,168 bytes. The larger erase block makes more efficient use of the silicon-die area by reducing decoding-periphery overhead. Although the new chip, which competitor Samsung (www.samsung.com) also offers, is pinout-compatible in 48-lead TSOPs with previous memories, the internal changes will require alteration of the corresponding hardware- or software-based memory controller.
Backward incompatibility is the root of the reason that Toshiba doesn't plan to offer 1-Gbit, SLC, NAND-based SmartMedia cards, which rely on a system-based controller, and believes its card partners will not do so, as well. Samples of Toshiba's 2.7V TC58010FT are now available at $80, and full production of the single-die, 1-Gbit device and samples of the dual-die, 2-Gbit variant are both scheduled for the first quarter of next year. (Samsung claims its 1-Gbit part is now in production.) Don't be surprised if you see MLC variants of the TC58010FT down the road, as well.
Toshiba, 1-972-995-2011, http://chips.toshiba.com.
