Using synthesis in the analog-design flow
Analog-synthesis tools can help speed the analog-circuit-design flow.
By Trent McConaghy, Analog Design Automation Inc -- EDN, January 24, 2002
Analog-synthesis tools provide great potential for speeding the design process for analog circuits. This capability is especially important in mixed-signal-system-on-chip design, in which the analog portion presents one of the biggest bottlenecks. Analog-synthesis tools also let you examine high-level analog-design trade-offs early in the design process. Frequently, they generate better performing designs that require less power and area.
An established flow for analog design starts with determining your design objectives. You then select a topology, set up testbenches and related simulations, and use feedback from simulations to configure the circuit parameters. If necessary, you perform layout and verification of the design and circuit reconfiguration. Figure 1 depicts the design flow for an analog-synthesis product. The flow is traditional enough to minimize the problems that might result from a drastic change to the established methods.
Using a schematic editor
You can begin your design using any schematic editor familiar to you. First, you need to set up testbenches and goals. Testbenches capture the measurements of circuit behavior; goals tell the synthesis tool how to treat the measurements—for example, to maximize them. Both are necessary to capture designer intent. You can use the testbenches for the class of circuit, such as a filter or PLL, that the synthesis-tool vendor supplies. Analog designers rely on their strong understanding of electronics when designing manually, but synthesis engines lack the insight necessary to avoid pathogenic circuits. Therefore, you must robustly define testbenches for synthesis tools. The tools must be able to handle a wider range of inputs, including "unreasonable" inputs.
You can modify the vendor-supplied testbenches or even create more testbenches using a schematic editor. The synthesis tool can readily accept new scalar measures of performance, computed via combinations of the schematic editor's "calculator" functions, such as addition, absolute value, phase, percent overshoot, and settling time.
Circuits need to operate in nonideal conditions, such as, for example, during changes in temperature, power-supply voltages, and loads. You can configure the synthesis tool to take into account sets of conditions, or corners, during synthesis. To do so, you must set up the varying conditions as parameters, and the synthesis engine will handle them in the same manner as it does the design variables.
You select the topology in the same manner as in the manual flow, based on experience and any past characterizations of topologies you have done. The decision is less critical than it was before the availability of analog synthesis, however, because feedback on the decision arrives sooner. The speed of the synthesis tool lets you quickly find out how useful your selection is, so you can switch topologies if necessary. Engineers refer to the selected topology as the circuit under test. You go through the schematic of the circuit under test and parameterize components, as desired, via the schematic editing tool's usual interface.
In parameterizing the circuit, you set up relations between design variables and actual physical parameters. The physical parameters are functions of design variables. For example, to set up a matching relationship between two actual resistances, R1 and R2, you could set up R1=x1, R2=x1·x2. The design variables are x1, a real number, and x2, an integer. The synthesis tool varies the design variables during a synthesis run.
Variations exist in the physical parameters of any circuit a manufacturer produces. Analog circuits are especially prone to such variations. Tactics that analog designers currently use to deal with these effects include matching and using safety margins for transistor-operating regions. A synthesis tool can also exploit these tactics.
However, these tactics cover only part of the robustness problem. A truer method is to directly take randomness into account. Designers can also run Monte Carlo analyses and may tweak their design parameters to improve robustness. Monte Carlo analyses use information from the "statistics" section of a netlist, which defines random variables. Each variable is defined by distribution type (for example, Gaussian), plus distribution parameters (for example, mean). You can also define correlations between variables.
You usually construct the statistics section using rules of thumb based on experience to describe component-level parameter variations, or you use a computer using fabrication data to describe variations in the models themselves. Both construction methods support process and mismatch variation. Using the information in the "statistics" section, the synthesis tool takes randomness into account. If you leave handling variations for the end of synthesis, the resulting designs could be in regions of design space that you cannot "locally" improve for robustness. Therefore, the tool deals with the variations during its execution.
An alternative tactic for dealing with randomness is via model corners. You can specify a model file with model corners and then set up a model "parameter" that switches among the corners.
Moving to synthesis tools
Once you set up the testbenches and circuit under test with the schematic-entry tool, you are ready to configure from within the synthesis tool. The tool lets you choose nominal, worst-case, or yield analysis; whether to analyze a single design; and whether to perform local or global optimization. The synthesis tool presents a view of the testbenches. With each testbench, you can see which simulation analyses are running, as well as the expressions to compute scalar measurements from the simulation outputs. Thus, you can select which testbenches to use for synthesis.
You need to add more information to the variables first specified in the testbenches and circuit under test. Variable come in three types: Design variables describe candidate circuit designs; environmental variables take into account operating conditions, such as temperature and load resistance, and are specific for each testbench; random variables are the variables described in the "statistics" section. You can choose to set each design variable to a constant value or a default value, or you can vary the value within a range of possible values. For each environmental variable, you can choose whether to use a constant value and the default value. You can also specify the "corners." A corner holds a value for each environmental variable, possibly including corners for models.
You tell the synthesis tool how to treat each performance measure; that is, whether to maximize, minimize, match a value, or pass a constraint threshold. You can also set the relative importance of each performance measure, thereby directing the synthesis tool to bias its search toward specific regions of performance space. You then specify which simulator to use within the synthesis loop and start the synthesis. The tool starts to return synthesis results within minutes. If results are unexpected, it may be because you wrongly configured something. For example, you may have neglected to use a particular testbench. In such cases, you can stop the synthesis run, make the fix, and then restart the process.
The tool presents you with a suite of results, organized in a tablelike form, and updates it at regular intervals. Each suite of results describes a whole set of candidate circuit designs that occupy the performance trade-off space. You can sort results, for example, based on a weighted sum or on a particular performance measure. For each candidate circuit, you can see its design variables and browse to see the circuit's performances for each combination of corner and random sample. The tool stores all of these results in a database that you can access via other programs.
A visualization tool provides another "view" of the results database. With the visualization tool, you can choose types of views, such as 2-D trade-offs, interactive 3-D trade-offs, and so on. You can use the tool to assess the impact of random and environmental variations and to home in on interesting designs. This view provides a useful window into the characterization of the topology, which will be helpful in future topology-selection decisions.
Many analog-design specifications are rough guesses, because you may not initially know the performance trade-off implications of hard constraints. The synthesis tool supports these rough guesses in a natural manner. During the course of a synthesis run, the synthesis tool provides you with a view of the performance trade-offs. You can use this fresh information to bias the synthesis search toward meeting higher priority specifications by altering the importance of each performance during the course of the run. This synthesis "steering wheel" allows you to dynamically alter your target circuit during synthesis.
You can readily make other changes to the run, as well. After stopping execution, you can change virtually anything that you configured. You can change variable ranges, freeze variables, change testbenches, change constraint thresholds, or change the type of run. The new run can easily use as seeds the results of the previous run or of other runs. You restart the engine to continue synthesis.
You can back-annotate synthesis results into the schematic editor to examine the performance of a candidate circuit in more detail and to pass those results on to the next stage of design. Once you select a design (a sized schematic), you proceed to layout and then extraction in the usual manner. You can then back-annotate the results from extraction into the schematic. You reverify performance by using either the simulator or the "analysis" option in the synthesis tool to leverage the complete set of testbenches that synthesis uses.
You may also perform a "local" synthesis on the topology that includes the annotated parasitics. However, doing so "refines" the design in light of the parasitics but does not greatly affect layout or the next parasitic extraction and may lead to another reloop through layout and extraction.
In the manual flow for sizing the circuit, engineers use an iterative process of setting design variables, running simulations, and viewing results. The synthesis tool sits between the schematic editor and the simulator, but it automates the iterative process. An analog-synthesis tool can bring the benefits of synthesis but fit seamlessly within the design flow.
