Logic offers complementary-switch control
Edited by Bill Travis
Yen-Hsu Chen, Analog Integrations Corp, Hsinchu, Taiwan -- EDN, December 6, 2001
The complementary-switch controller in Figure 1 uses a few inverter gates to provide drive signals for the complementary switches. Complementary-switch configurations find widespread use in synchronous-rectification circuits, charge pumps, full-bridge control circuits, and other circuits. The circuit in Figure 1 provides not only a complementary drive signal but also a deadtime delay on both rising and falling edges. The high-speed inverter gates use IC1, a 74HC04 CMOS circuit, and 1N5819 Schottky diodes D1 and D2. The 74HC04 inverter features symmetrical input thresholds, VIHMIN and VILMAX, at 70 and 30% of the supply voltage, respectively. In Figure 1, IC1A inverts the signal at Node A to produce 
. When rises, C1 rapidly charges through D1. Output B drops immediately because of IC1B's inversion. However, Output C drops after a delay time that R2 and C2 determine because D2 is reverse-biased. The following formula gives the delay time, t1 (Figure 2):
When falls, C1 discharges through R1. Output B rises after a delay time that R1 and C1 determine. C2 discharges rapidly through D2, and output C rises immediately. The following formula gives the delay time, t2:
By inverting C, IC1D can provide 
a signal with the same polarity as B. By selecting values for R1, C1, R2, and C2, you can program the delay times. The delay can be as short as 50 nsec and as long as several milliseconds. This range provides flexible, optimized control for target devices. R1 and R2 should be larger than 2 kΩ because of the limited current available from the inverter IC.
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