Programmable-logic alternatives offer similar attributes but differing foundations
By Brian Dipert -- EDN, January 24, 2002
Actel promises that, with its ProASIC Plus FPGAs, it won't suffer the excruciatingly long announcement-to-production delay that plagued the first-generation ProASIC products' developer, Gatefield, which Actel has now acquired and which began touting the product in late 1996. Actel builds ProASIC Plus on partner UMC's (www.umc.com) 0.22-micron process, versus the 0.25-micron Infineon (www.infineon.com) process it used for ProASIC. ProASIC Plus has the same logic-cell structure as its predecessor. The biggest difference, as is also the case with competitors' generation-to-generation progressions, is the disproportionately increasing amount of on-board memory.
ProASIC Plus chips contain two to four times more of SRAM than the company's ProASIC precursors with equivalent logic-cell counts. ProASIC Plus also adds two 240-MHz PLLs and expands the number of protocols that the I/O buffers support. The $199 (100,000), 1 million-system-gate APA1000 has 56,320 registers, including those in I/O buffers, and 202,752 bits of embedded RAM. It is now available in sample quantities and will enter production in the second quarter, along with the APA750. Rounding out the family are 150,000-, 300,000-, 450,000-, and 600,000-system-gate parts, which will become available in the third quarter. Actel also offers a $600 onboard programmer and $1000 evaluation board.
Xilinx's CoolRunner-II, like ProASIC Plus, is single-chip, nonvolatile, and in-system-updateable. However, Xilinx built CoolRunner on an EEPROM platform, whereas Actel built ProASIC Plus on flash memory. Also, whereas ProASIC Plus is a fine-grained distributed-routing FPGA, CoolRunner-II is a coarse-grained CPLD. Intended as the successor to Xilinx's XC9500 family and XPLA3, which the company acquired from Philips, CoolRunner-II migrates XLPA3 to a 1.8V, 0.18-micron lithography. In the process, it tackles one key limitation of XPLA3: the chips' slower performance—albeit with much lower power consumption—than sense-amp-based alternatives from both Xilinx and other suppliers, such as Altera (www.altera.com) and Lattice (www.lattice.com).
Xilinx claims less-than-100-µA standby current for CoolRunner-II, along with 7.2 mW typical active power draw. The company measures this power on a 128-macrocell chip containing eight 16-bit, 50-MHz counters; therefore, 12.5% of the internal registers are toggling each clock cycle. Propagation delays are as low as 3.5 nsec for the 32-macrocell version and 6 nsec for the 512-macrocell part, coupled with 300-MHz clock frequencies. All family members offer 2×clock multipliers at each macrocell; 128-macrocell and larger CoolRunner-II devices also include a 2× to 16× on-chip clock divider.
CoolRunner-II I/O-buffer-voltage options are 1.5, 1.8, 2.5, and 3.3V; 32- and 64-macrocell parts contain one I/O bank. The 128- and 256-macrocell versions offer dual I/O banks that can run at independent voltages, and the 384- and 512-macrocell version supplies four I/O banks. The 64-macrocell part, now in production, costs $1.90 (100,000), and the company will release 32-, 128-, 256-, and 512-macrocell devices to production by the end of the first half. Version 4.1i of Xilinx's Integrated Software Environment tool set supports all CoolRunner-II devices (Picture).
Actel, 1-408-739-1010, www.actel.com.
Xilinx, 1-408-559-7778, www.xilinx.com.
