EDN Access -- 03.17.94 Synchronized regulator produces coherent noise

Jim Williams, Sean Gold, and Steve Pietkiewicz, Linear Technology, Milpitas, CA -- EDN, March 17, 1994

Design Ideas: March 17, 1994

By using a gated-oscillator architecture instead of a clocked-PWM one, gated-oscillator-type switching regulators permit high efficiency over extended ranges of output current. This architecture eliminates the housekeeping currents associated with the continuous operation of fixed-frequency designs. Gated-oscillator regulators simply self-clock at whatever frequency is necessary to maintain the output voltage. Typically, loop-oscillation frequency ranges from a few hertz to the kilohertz region, depending on the load.

In most cases, this asynchronous, variable-frequency operation doesn't create any problems. However, some systems are sensitive to the asynchronous characteristics. The system in Fig 1 slightly modifies a gate-oscillator-type switching regulator by synchronizing its loop-oscillation frequency to the system's clock. The oscillation frequency and its attendant switching noise, albeit variable, become coherent with system operation.

To analyze the system in Fig 1, temporarily ignore the flip-flop, and assume the circuit directly connects the A_OUT and FB pin of the LT1107 regulator. When the output voltage decays, the set pin drops below V_REF, causing A_OUT to fall. The internal comparator then switches to high, biasing the oscillator and output transistor into conduction. L1 receives drive pulses, and the circuit deposits this inductor's flyback events into the 100-mF capacitor via the diode, ultimately restoring output voltage. This action overdrives the set pin, causing the IC to switch off until it requires another cycle. This oscillator cycle's frequency is load-dependent and variable.

Now, interposing a flip-flop into the path between the A_OUT and FB pins, as the figure shows, synchronizes the regulator to the circuit-generated clock. When the output decays far enough, the A_OUT pin goes low. At the next clock pulse, the flip-flop's Q₂ output sets low, biasing the comparator-oscillator. This turns on the power switch, which pulses L₁. L₁ responds in flyback fashion and deposits its energy into the output capacitor to maintain output voltage. This operation is similar to the previously described case, except that the flip-flop now synchronizes the sequence of events with the system clock. Although the resulting loop's oscillation frequency is variable, the frequency and all attendant switching noise is synchronous and coherent with the system clock.

The circuit requires a start-up sequence because the output provides power for the clock. The circuit connects the flip-flop's remaining section as a buffer to furnish start-up. The flip-flop's connected CLR₁ and CLK₁ lines monitors output voltage via the 221-, 82.5-, and 100-k Ohm resistor string. When power is applied, Q₁ sets CLR₂ low, which permits the LT1107 to switch, thereby raising the output voltage. When the output goes high enough, Q₁ sets CLR₂ high, and normal loop operation commences. Although this circuit uses a step-up regulator, the technique also works with other types.

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