Two gates expand ASIC's memory-decoding range
Vinh Hoang, Ericsson Inc, Brea, CA -- EDN, March 29, 2001
Many electronic circuits implement chip-select lines on an ASIC. From the beginning of the design cycle, the chip selects, CS0 to CS4, have defined bases on the memory map (Figure 1). Adding functions to the product requires increasing the DRAM space. Now, you must redesign the ASIC so the chip select, CS1, can accommodate the new memory space of 04000000 to 0BFFFFFF.
The circuit in Figure 2 uses two external exclusive-OR gates to expand memory-address-decoding space for the CS1 signal from the initial range of 04000000 to 07FFFFFF to 04000000 to 0BFFFFFF. When address line A27 is low, exclusive-OR gates IC1A and IC1B allow A27 and A26 signals to pass through unchanged. In this case, the ASIC decodes the address range 04000000 to 07FFFFFF, according to the existing memory map. However, when address line A27 is high, which accesses the address range 08000000 to 0BFFFFFF, both IC1A and IC1B act as inverters. Thus, the circuit inverts lines A26 and A27, so that the ASIC now sees the address range 04000000 to 07FFFFFF instead of 08000000 to 0BFFFFFF. The function of the exclusive-OR gates is to map the CS1 selected address range of 08000000 to 0BFFFFFF to 04000000 to 07FFFFFF.
