Shuttle gets less risky and less expensive
-- EDN, January 18, 2001
UMC's Silicon Shuttle program lets you verify your advanced designs and prototypes in silicon, helping to minimize risks and costs. The program provides wafers dedicated to mixed-mode and RF CMOS as well as to the 0.13-µm WorldLogic platform. Each customer purchases "seats" on a mask, reducing individual customer costs.
The UMC "hot-lot" schedule is approximately one day per photolithography layer, enabling fabrication times of less than four weeks for six-layer-metal, 0.18-µm wafers. The company plans this year to announce several 0.13-µm WorldLogic Silicon Shuttle wafers for logic and mixed-mode technology. The WorldLogic platform provides full copper/low-k interconnection technology and transistor-switching delays of less than 10 psec, enabling microprocessor-clock frequencies greater than 1 GHz. Furthermore, UMC will offer extensive analog options on several dedicated 0.13-µm mixed-signal wafers. These options include UMC metal-insulator-metal capacitors with good Q-values, low-threshold-voltage transistors, and copper inductors.
Several Silicon Shuttle options, including low-voltage/temperature transistors, metal-insulator-metal capacitors, and inductors, are also available for Bluetooth. UMC has worked with Bluetooth OEMs and intellectual-property creators to develop RF CMOS technologies that will make Bluetooth chips more cost-effective than the BiCMOS technology that Bluetooth samples currently use.
UMC, www.umc.com.
-by Gabe Moretti
