Simple technique improves transient dynamics
Robert Sheehan, Linear Technology Corp, Milpitas, CA -- EDN, June 24, 1999
Designing low-voltage, high-current converters with fast dynamic performance places stringent demands on a system designer. However, a simple technique reduces the peak voltage deviation and decreases the response time for a transient load step (Figure 1). This circuit converts 48V dc to 1.5V at 15A using a two-transistor forward converter with synchronous rectifiers. Q1 and Q3 are primary-side switches. Q2 and Q4 are the secondary-side rectifiers. IC1 and IC2, a pair of dual MOSFET drivers, provide the gate drive. The circuit derives the power for IC2 by rectifying the peak secondary voltage. This feature, which allows IC2 to operate with a 6V supply instead of a 12V supply, reduces gate-drive losses without any significant increase in rectifier conduction losses. IC3, a high-power, synchronous switching-regulator controller, is at the heart of the PWM control. R1 and C1 set the oscillator frequency to just under 200 kHz and limit the maximum duty cycle to 50%.
IC4, a programmable reference, functions as an error amplifier, overriding IC3's internal gm amplifier. This design feature allows for greater control in tailoring the frequency-response characteristics and provides much greater accuracy. You can implement an added feature for output-voltage programming using the summing junction at the REF pin node. Differential amplifier IC5A allows real remote sensing of the output voltage and makes it possible to produce output voltages well below the 2.5V reference of IC4.
The circuit configures C2, R2, and C3 in a classic Type 2 feedback-amplifier network. The center oscilloscope trace in Figure 2 shows the response to a 100-nsec load step of 5 to 15A (100A/?sec). The peak-to-peak deviation is 96.8 mV with a settling time of approximately 40 msec.
Modifying the feedback network can produce significant improvement. Shorting C2 with S1 limits the dc gain of the error amplifier, causing the output voltage to deviate ±15 mV around its nominal value at half-load. This modification programs the output voltage to move slightly in the direction in which it already wants to go when the load steps. This change also removes the long tail in the settling response because there is no RC charging in the error-amplifier feedback path. The improvement is dramatic, as the top trace in Figure 2 shows. The peak-to-peak deviation decreases by 30% to 66.4 mV. The full-load-to-light-load settling time decreases to 20 ?sec. The light-load-to-full-load settling time is virtually instantaneous. (DI #2370)
