FPGA implements X.50 Division 3 recommendation
Andres Martinez, Alcatel, Ramirez de Prado, Spain -- EDN, April 13, 2000
The scheme in Figure 1a uses five delay cells and an XOR gate to configure the data stream for the X.50 Division 3 recommendation of ITU-T. The X.50 recommendation defines the fundamental parameters of a multiplexing scheme for interworking data networks using different envelope structures. Division 3 applies to the interworking between two networks, both of which use the 8-bit envelope structure. X.50 recommends a pattern of 19+1 bits, which the following primitive polynomial generates: 1+x2+x5. With this polynomial and the initial conditions, Table 1 generates the pattern 01110. The polynomial does not directly generate the first value, A, in the table because this value depends on the rest of the system. The scheme in Figure 1a is typical of a scramble, and is one part of a transmitter/receiver system for data communications. You can implement Figure 1a in a 30,000-gate FPGA.
It is important to set the delay cells to the correct initial value. For this design to achieve the correct data stream, the initial data should be 0010110. The use of a 7-bit word for the initial data enables you to change the design to X.50 Division 2 by changing only the initial word and the position of the XOR gate. The process for achieving the polynomial is as follows:
|
The clk signal is not exactly a true clock signal. This design uses a 244-nsec-wide clock pulse and a 125-µsec period. Rising edges generate the interval number, and falling edges generate the data out. Because 244 nsec is much less than 125 µsec, data out is present in all intervals. Click here to download the source file. The timing diagram in Figure 1b shows the resultant data. (DI #2509)
