VHDL customizes serializer/deserializer
Antonio Di Rocco, Siemens ICN, L''Aquila, Italy -- EDN, June 5, 2000
Many applications require a multiple-signal exchange among cards through a backplane. Several solutions are available to serialize/deserialize data—from the classic UART to newer low-voltage differential-signaling components. It is sometimes important to have hardware flexibility in transferring signals; for example, you can use a PLD to implement a UART-like function to perform a parallel-serial-parallel conversion (Figure 1). Figure 2 shows the frame structure. The idle "1" bits exactly fill the time between the start and stop bits. Assuming fBIT=1/TBIT as the speed of the serial link, the sampling frequency, fSH, for each parallel-input channel is fSH=fBIT[(N+3)/2]. With an internal state machine working with a system clock (clk), each eight-clock period corresponds to one bit period, TBIT. The relationship between sampling frequency fSH and the PLD clock is fSH=[fCLK(N+3)]/4.
he deserializer does not perform a clock-recovery function but works with the nominal clock frequency of the transmitter side. Jitter tolerance on the serial line is related to the number of parallel-input channels. During the time between the start bit and the stop bit, the system tolerates a delay time of 3/8TBIT. Often, system features are related to the maximum speed the serial link allows. To improve the quality of transmission, you can insert a more complex CRC function. The timing simulation shows a serialization of N=32 signals using a sampling frequency fSH=17.8 kHz, which corresponds to a PLD clock fCLK=10 MHz with a speed of 1.25 Mbps on the serial link (Figure 3). Note that the serializer's start bit occurs just as the master reset (mr_rx) is deasserted. On the receiver side, the deserializer has its master reset (mr_rx) deasserted while it receives a frame; thus, it starts to sample a wrong frame. Between the two first start_frame_rx pulses, no valid_data pulse exists. The frame-acceptance pulse appears at the end of the second received frame. You can easily customize the VHDL code. It uses the ser2par.vhd and par2ser.vhd component source files. Another VHDL listing has the package source file, in which the constant N designates the number of parallel channels. Finally, a "bench" routine, bench.vhd, runs simulations. Click here to download the VHDL listings. (DI #2542).
