Implementing power management for instantly available PC cards
Enabling a PC to respond to important stimuli, such as incoming faxes, while it appears to be off to save energy, presents some intriguing power-system-design challenges.
Fabien Franc, California Micro Devices -- EDN, January 6, 2000
Instantly available PCs (IAPCs) are creating new power-management requirements. You can provide the continuous 3.3V output necessary to support PCI cards in such PCs. After a quick introduction to PC and PCI-card power requirements, you can learn how to avoid supply-voltage discontinuities during critical power transitions. A detailed performance analysis explains the measured power-up and -down transient response of several hardware configurations. The analysis illustrates the effect on performance of variables such as voltage-regulator hysteresis, decoupling-capacitor values, power-supply line series resistance, and load current.
What is an instantly available PC?
Today, PCs need to remain constantly connected to the outside world but, at the same time, consume minimal power. Even when a computer appears idle, it must still receive e-mail messages and incoming faxes or phone calls. The PC must automatically switch from sleep mode to on mode; in other words, it must be instantly available. The challenge is to maintain a system's modem or LAN connection while minimizing power consumption. These power-management features are called wake on ring (or wake on modem), wake on LAN (WOL), and wake on power-management event (PME).
The main qualities and benefits of such systems are that the PC is available any time to receive messages; the PC responds any time, allowing you to perform operations such as maintenance; and the PC saves energy by being silent in the idle mode.
Microsoft's OnNow initiative defines requirements for many PC hardware and software components, including the Windows operating system, software applications, device drivers, and system hardware. All of these elements must work together to provide a fully transparent power-management system. This article focuses only on the hardware aspects.
ACPI system design
An IAPC appears to be off, yet it can snap back within seconds to its full-ready state, for example, responding to a ringing phone in time to service a call. To meet these requirements, Intel, Microsoft, and Toshiba defined the Advanced Configuration and Power Interface (ACPI) Specification.
Instantly available motherboards include an ACPI BIOS, an ACPI chip set, and PCI slots that comply with the PCI Bus Power Management Interface Specification Version 1.1. An Intel chip set supports the power-management features that define the ACPI sleep states and also generates the signals that control power planes and turn the main power supplies on and off.
The implementation includes multiple power sources and uses separate power planes in the system. The state that the system demands determines which power source is active. One of the major requirements is to automatically and repeatedly switch between power sources without interruption.
The sleep state of an IAPC is called "suspend to RAM." To implement this state, the system uses split power planes and an auxiliary power source (VAUX) for dual-mode power distribution. By definition, all PCI add-in cards connect to the motherboard through the PCI bus. The PCI connector reserves several pins to support instant availability.
On newer PCs, three independent voltage sources are now available on the PCI bus: 3.3VAUX, 3.3VCC, and 5VCC. In a power-plane partitioning system of an IAPC, 3.3VAUX is always electrically isolated from the main PCI 3.3V rail. During normal operation, the 3.3VAUX supply remains on, whereas the system can switch the other main supplies, 3.3VCC and 5VCC, on and off as needed.
PCI cards
PCI network-interface cards (NICs) and modem cards use split power planes. To operate in sleep mode and wake up the system, these cards require only the VAUX power supply. Some NICs that operate in wake-on-LAN mode get 5V standby power through a cable that connects directly to a header on the motherboard.
Today, PCI-card chip sets and ASICs operate at 3.3V, so their power consumption is much lower than that of older 5V modem chips. However, older PCs still supply 5V and do not have a 3.3VAUX supply. To ensure compatibility with both old and new PCs, newer PCI cards operating in PCs that lack a 3.3V supply derive their own 3.3V regulated power from the system's 5V supply. The PCI Power Management Specification limits the output current of such 3.3V regulators to 375 mA.
Hysteresis
Hysteresis voltage, VHYSTERESIS, is the difference between the enabling threshold (at which the regulator turns on) and the disabling threshold (at which the regulator turns off) (Figure 1). VHYSTERESIS establishes the maximum level of acceptable noise or disturbance on VCC or VAUX. Noise susceptibility is critical during power transitions.
As shown in Figure 2, the voltage that the device sees is given by:
VCCIN=VCC–(RSI)–(RTI)–(LTdI/dt) , (Equation 1)
where VCC is the power-supply voltage, RS is the power-supply output impedance, RT is the interconnect series resistance (between supply and regulator), LT is the trace (line) inductance (between supply and regulator), and I is the current.
Assuming an ideal situation in which there is minimal parasitic inductance, the hysteresis level should follow:
VHYSTERESIS>(RS+RT) I. (Equation 2)
The worst-case condition, with respect to the inrush current, occurs at turn-on, when the initial output-capacitor voltage is zero. During turn-on, the current rises from zero to a high value. The inrush current is highest when the initial output-capacitor voltage is zero. Higher capacitor values also increase inrush current. You can assume an inrush current equal to twice the device's maximum dc load current. An inrush current of 1A and a hysteresis of 250 mV give a maximum recommended series resistance of 0.25W (Equation 2).
Power regulators
Today, several companies offer low-dropout regulators that provide a fixed 3.3V output with a current load exceeding 375 mA. These products also feature an intelligent controller that allows either a 5V supply or an auxiliary 3.3V supply to supply power to the 3.3V load via an external switch. California Micro Devices, Cherry Semiconductor, and Semech all offer regulators that satisfy the demanding requirements for uninterrupted and reliable power (Table 1).
The CMPWR150 from California Micro Devices can supply as much as 500 mA of continuous output current when it operates from a 5V VCC. Figure 3 shows the test setup used during transient characterization of this IC. The setup uses an external P-channel MOSFET to switch the 3.3V VAUX at full-load current. Figure 4 shows how improper implementation of the test circuit can produce oscillation at the regulator output.
The circuit compares the VCC input to a 4.1V internal-threshold level. Whenever VCC drops below that level, the regulator is disabled and the DRIVE output is enabled (active low). The DRIVE output controls an external P-channel MOSFET switch, which connects an auxiliary 3.3V source to the load. When the regulator is enabled, the DRIVE output is set to VCC.
The setup includes the VCC supply's effective source impedance, RS, which is approximately 0.2W. As measurement data later demonstrate, this impedance should be no greater than 0.25W to ensure that precise switching is maintained during VCC selection and deselection.
During VCC power-up/down sequencing, the test setup controls both the rise and fall times to maintain a 20-msec duration. This switching time represents the worst case in most applications. During characterization, the maximum load current is 500 mA unless otherwise specified.
When you perform the transient analysis for the VCC power-up and power-down sequences, VAUX normally equals 3.3V—its nominal value. A cold-start power-up occurs when VC rises from 0 to 5V with VAUX connected to ground (Figure 5). As soon as the 5V source reaches the regulator_enable threshold (4.25V typical), the regulator turns on. At that time, the voltage across the output capacitor begins to rapidly charge, pulling a large transient current, which can easily exceed 1A. It is, therefore, important to consider the parasitic series resistance and parasitic inductance between the supply voltage, VCC, and the device. Equation 1 gives the voltage that the device sees. Clearly, a large, rapidly changing current creates a large change in VCCIN. If the input level drops below the regulator_disable threshold (4.1V typical), the regulator turns off. The input level then starts to rise back toward 5V, turning the regulator back on. This situation results in an unstable state ("motorboating"). The regulator turns on and off until it has finally charged the output capacitor to 3.3V.
Capacitors
Minimizing this effect requires an input capacitor in close proximity to the VCC input pin. When a transition occurs from VAUX to VCC, the capacitor serves as a charge reservoir to provide some of the load current (Figure 6). This function is especially critical when the output capacitor is not yet charged at power-up or when the output level is much lower than 3.3V. The regulator goes into current limiting until VOUT returns to its nominal level. The input capacitor should be a tantalum device of 1 WF or more.
During power transitions, a previously charged output capacitor provides the load current until the regulator or the auxiliary supply takes over (Figure 7). A tantalum capacitor of 10 WF or more at the output improves this transition.
Additionally, you should place ceramic chip capacitors of 0.1 WF next to both the input and the output pins to reduce high-frequency noise.
Conclusion
IAPCs require specialized power-management devices to provide regulated voltage sources and smart switches among power sources. High-performance integrated devices are ideal because they reduce component counts and simplify design and manufacturing start-up. These products allow interface-card manufacturers to meet IAPC power requirements.
Author info
Fabien Franc is a senior application engineer at California Micro Devices. He has an MSEE from École Polytechnique Federale (Lausanne, Switzerland), and he is a member of the development team for power-management products at California Micro Devices. "Instantly Available Power Managed Desktop PC," Design Guide, Rev. 1.2, Sept 25, 1998, Intel Corp.
REFERENCE
1. "Instantly Available PC System Power Delivery Requirements and Recommendations," Revision 1.0, Dec 30, 1997, Intel Corp.
2. "PCI Bus Power Management Interface Specification," Revision 1.1, Dec 18, 1998, PCI Special Interest Group.
