Merced Meets AMD's SledgeHammer
Intel's new direction draws praise and pans
By Arik Hesseldahl -- EDN, October 11, 1999
San Jose-On the day it pulled the wraps off some of its plans for its long awaited 64-bit architecture at the Microprocessor Forum here, Intel Corp. couldn't have helped but notice the SledgeHammer in the hands of arch-rival Advanced Micro Devices Inc.
As Intel last week began to reveal the first details of its long-awaited Merced, which it has renamed Itanium, (pronounced like titanium), AMD produced its own set of plans for a 64-bit architecture that will extend the x86 instruction set into the 64-bit realm. Analysts said Santa Clara, Calif.-based Intel may have something to think about in AMD's approach.
Harsh Sharangpani, Intel's principal engineer on the Itanium project, presented Intel's plans, which embrace a new design philosophy the company called explicitly parallel instruction set computing (EPIC). Intel plans on aiming chips based on the technology at the server and workstation market. Production is expected to begin in mid-2000.
Most of the questions surrounding Intel's approach centered not on how it will perform at 64-bit computing, but on how it will work with standard 32-bit code. Intel's plans call mainly for running 32-bit code in the chip's enhanced compilers. This is likely to slow performance when running 32-bit applications and operating systems.
"Intel is saying that its 32-bit performance will be okay, but it won't be great," said Nathan Brookwood, principal analyst with the market research firm Insight 64, Saratoga, Calif. "Intel set expectations that x86 performance in Itanium will be comparable with current mainstream 32-bit processors. But for anyone interested in leading edge 32-bit performance, Itanium is not going to be as fast as the 32-bit optimized processors."
In contrast, AMD's SledgeHammer extends the existing x86 architecture to the 64-bit realm. The key allure of SledgeHammer is that it will be able to run all existing 32-bit applications and operating systems, without recompilation.
With Intel's new direction in the 64-bit space, rival AMD sees an opportunity to capitalize on some of the chief software-related complaints about Itanium.
"Intel is going in a completely different direction, which we see as opening up the playing field," said Fred Weber, vice president of engineering for the Computation Products Group of AMD, Sunnyvale, Calif. "Now I don't think we're going to be in big servers overnight. But it wasn't so long ago that Intel wasn't in servers and I'm not saying we're going to do this alone. Some of the big server companies are going to have to do this with us and see it as a strategic move. But we're offering a very compelling solution."
Brookwood envisioned a situation where both Intel and AMD succeed in their approaches. If that happens, Brookwood said, AMD would arguably have the better solution because it preserves more readily the 32-bit environment without requiring more programming hoops to jump through. This could lead to AMD aiming the SledgeHammer chip at high-end desktop PCs, should AMD choose to market 64-bit computing as superior, he said.
Itanium's radical departure from the x86 architecture that Intel has adhered to also spurred discussion at the Microprocessor Forum. The forum's final panel discussion on Wednesday descended at one point into a debate over Intel's approach.
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| RAGE AGAINST THE MACHINE: Martin Hopkins, an IBM Fellow, speaks on a panel on the future of microprocessor design at last week's Microprocessor Forum held in San Jose. Fred Weber, vice president of engineering for AMD's Computation Products Group, looks on. |
"This has been the longest striptease in history," said Martin Hopkins, an IBM fellow, and one of the lead architects on IBM's 801 RISC processor. "We're all waiting with baited breath for Merced, and of course what we've all been told is that we're going to have wait for McKinley (Intel's second-generation 64-bit microprocessor) and I suspect that when McKinley comes in we'll be told to wait for whatever comes after that."
"I really have to compliment the Intel guys on this machine," Hopkins said. "There are lots of clever ideas in this machine."
But he said that "Hopkins' Law," no clever idea in computer architecture ever goes unpunished, still stands.
The problems with EPIC, as Hopkins sees them, deal with losing performance on multiple fronts, including pipeline length, frequency and cycles per instruction. EPIC's extensive use of prediction increases the pipeline length and slows performance, Hopkins said. These shortcomings cannot be made up in other areas, he added.
Fred Pollack, Intel's director of Microprocessor Research acknowledged that the pipeline length in Merced turned out to be a little longer than the company had envisioned.
"That is the struggle you have in the first implementation of an instruction set architecture," Pollack said.
Pollack defending the choices Intel made in EPIC, saying, "But the key thing here is that instead of doing all the dynamic predication and speculation, by making that more visible and under compiler control, it does allow you to have fewer compiler stages than you would otherwise need."
Hopkins further attacked the new Intel chip as a "benchmark machine."
"What we should be trying to do here is helping programmers," Hopkins said. "And here is a machine that requires you, just before you ship your application, to gather up a representative set of test cases, run the application, get the profiling, recompile everything, test it out again and then ship. This is a world where it's hard to even get programmers to use the optimize option on the compilation. It's absolutely unconscionable what Intel is doing."
