Clock-source jitter: A clear understanding aids oscillator selection
The signal edges in a digital data stream never occur exactly when the system expects or wants them. Defining and measuring the timing accuracy, or jitter, of those edges is critical to the performance of synchronous communication systems.
Joseph V Adler, Vectron International -- EDN, February 18, 1999
 Continuous advances in high-speed communication and measurement systems require higher levels of performance from system clocks and references. Performance that was acceptable in the past may be insufficient to support high-speed synchronous equipment. One of the most important and least understood measures of clock performance is jitter. The International Telecommunication Union defines jitter as "short-term variations of the significant instants of a digital signal from their ideal positions in time" (Figure 1 and Reference 1). Jitter can degrade system performance, and a clear understanding of both jitter frequency and amplitude is essential to correctly specify the performance you need from a frequency source. Familiarity with the practical methods of measuring jitter, including the relevance, limitations, and ease of each method, will help you follow some simple guidelines for specifying high-speed clocks and related devices. With these guidelines, you can determine a cost-effective clock-generation approach for each application. Good jitter performance and low cost are not mutually exclusive if you define the system's jitter requirements in amplitude and spectrum and if the clock-generation method is optimal for the application. Jitter affects system performance Books are available that thoroughly discuss the effects of jitter on communication systems (references 2 and 3), but a simple discussion can quickly elucidate the deleterious effects of jitter. All synchronous communication systems sample the value of every bit of transmitted data at the receiver. The sampled data can have only the value of logical one or zero. The optimum point for sampling data is at the center of each transmit clock cycle. To perform this function, the receiver aligns its clock with the transmit-data clock. Figure 2 depicts ideal, typical, and corrupted data streams. Each of these "eye" diagrams is a cumulative graphical portrait of the edge placement due to noise or jitter. Ideally, sampling occurs at the center of the eye. As edge jitter increases, the eye closes. As a result, the likelihood of an error—mistaking a logical one for a zero—increases. In a telecomm system, jitter due to oscillator noise is only one source of jitter, and designers of these systems must consider many sources of noise (references 1 and 4). For most systems, the jitter that a clock source introduces is only one component of noise and only one part of an error budget that you must weigh against performance requirements and cost. Define jitter It is important to understand the definitions of jitter and the quantitative ways that you can express jitter. For example, pattern, or pattern-dependent, jitter is sometimes called "flanging." This type of jitter is not random; it generally results from subharmonics. When you view this type of jitter in the time domain, it appears as multiple modes of jitter. Pattern jitter is deterministic jitter that you can attribute to a unique source. All other jitter that this discussion refers to is stochastic in nature, and you may describe it only as a random variable with respect to time. You can quantitatively express jitter in the following ways:
As an example of these units, consider a clock rate of 155.52 MHz. One UI equals the period of the signal, which you can then translate to time and degree units as follows: 1/155.52X106 UIs=6.43 nsec=360°. In this case, 100 psec of jitter=0.01555 UIs=5.598°of peak-to-peak jitter. All three numbers describe the same amount of jitter. To define jitter power, you typically use rms, 1-sigma (  ) measurements. A reasonable expectation of peak-to-peak jitter, and a standard industry number, is approximately 7, or seven times the rms value. For the above case of 100-psec jitter, you find the rms jitter power by dividing the peak-to-peak jitter by seven and then squaring the result: 0.01555/7)2=0.0000049 UI2. Expressed in decibels relative to one unit interval (dBUI), jitter power in this case is 10log(0.0000049)=–53.1 dBUI. Table 1 presents these various measures of jitter for a 155.52-MHz system clock. You can also derive jitter from power-spectral-density, or phase-noise, measurements.Jitter bandwidth and spectral content The displacement of the edges in Figure 1 is a result of noise. Noise has spectral content as well as power. Consequently, the edge jitter in Figure 1 also has spectral content, and the edges in the figure vary randomly with time. However, the noise that causes the jitter is not necessarily uniform over all frequencies. Jitter due to 10-kHz noise can be greater than or less than jitter due to 100-kHz noise. The spectral content of clock jitter differs greatly depending on the clock-generation technique. Measured jitter also varies with measurement technique and jitter bandwidth. Improperly specified or measured jitter might result in unnecessary costs, or poor system performance. A true measure of clock jitter is the accurate position of clock edges over time. The most direct method of examining the placement of edges is to look at the edges using an oscilloscope. Unfortunately, you can't use standard oscilloscope techniques to identify individual clock edges in absolute time. Any jitter that a standard oscilloscope measures is due to trigger instability. As a result, direct-waveform measurements using an oscilloscope—even a very good oscilloscope—are not valid measurements of jitter. An alternative technique can locate the reference edge, discriminate with time, and examine the jitter on following edges (Figure 3). This technique connects the output of the unit under test to a delay line/splitter, the Tektronix DL-11 (www.tek.com). The nondelayed output of the splitter drives the external-trigger input of the oscilloscope, in this case, a Tektronix CSA-803 communications analyzer. The delayed output of the DL-11 connects to the input of the oscilloscope. The technique locates the trigger edge by examining the clock stream at a length of time after the trigger that equals the delay, which in this case is 47 nsec. After identifying the trigger, the test examines the next edge and produces a histogram of the measured jitter of the second edge. The technique relies on the statistical and histogram capabilities of the CSA-803. The limits of this useful technique depend on the length of the delay line,  d, and the speed and sensitivity of the oscilloscope. For all frequencies greater than 1/(2 d), the noise of the oscilloscope limits the measurement. At less than 1/(2d), the sensitivity drops by approximately 20 dB/decade. For the 47-nsec delay in Figure 3, the corner frequency occurs at 3.3 MHz. Using the CSA-803, the technique can resolve all jitter due to frequencies greater than 3.3 MHz to approximately 5 psec. Jitter at 330 kHz is unresolvable at less than 50 psec. Similarly, the technique cannot measure 33-kHz jitter at less than 500 psec.The sensitivity of the system is a function of jitter frequency according to the following equation:  where Sens(f) is the jitter sensitivity, d is the amount of delay, f is the jitter frequency you want to measure, and r is the oscilloscope resolution.Figure 4 is a plot of this equation using a 47-nsec delay line. It is critical to understand the advantages and limitations of this measurement method. For the current numerical example, the plot indicates that low-frequency jitter of less than 300 kHz is unobservable. Conversely, you can easily identify jitter due to sidebands at an offset of 3 MHz or more. This test method is appropriate when measuring oscillators that employ direct frequency multiplication or for cases that don't need to consider low-frequency jitter, such as pattern jitter. Measure jitter with a PLL The previous example points out that the length of the delay line limits resolution when measuring edge jitter. To measure jitter below a 100-Hz offset would require approximately 300 miles of very-low-loss delay line. In lieu of such a ridiculous requirement, PLLs are useful for a variety of noise measurements. Figure 5 shows the basic elements of a PLL for measuring the noise of a clock source. (References 5, 6, and 7 are three excellent references for understanding PLLs.) Measuring clock-induced noise places many requirements on the PLL. The PLL loop bandwidth is a critical parameter for successful measurements. The system measures only jitter frequencies higher than the loop bandwidth. The loop bandwidth should be a maximum of one-tenth of the lowest jitter frequency of interest. Loop damping must be at least five to reduce jitter peaking in the PLL; jitter peaking increases measured jitter. The ITU and Bellcore specifications include recommended jitter bandwidths for the measurement filter (references 1 and 4). For any valid measurement, you first define the bandlimiting. Finally, the output of the phase detector is a varying dc signal that is proportional to the varying phase due to jitter. It is necessary to know the gain constant (Kd) of the phase detector in volts per radian to quantify the detected jitter. For example, a phase detector in which Kd equals 1 mV/° has a peak-to-peak output of 10 mV for an oscillator with 10° of peak-to-peak jitter. You may need to inject a known amount of jitter to calibrate the system for accurate measurements. Interpret the PLL data The time-domain output signal of the phase detector in Figure 5 contains a wealth of information about the jitter of the measured clock. Direct examination of the signal using an oscilloscope can show peak-to-peak jitter. You can also use a true rms voltmeter to measure rms (1 ) jitter. For these measurements, it is critical that the measurement filters you use represent the band of jitter frequencies of interest; it is senseless to measure noise from dc to 10 MHz when the intended system has a bandwidth of 10 kHz to 1 MHz. Oscilloscopes with histogram and statistical capabilities are also useful for characterizing the measured jitter.The frequency-domain spectrum of the output signal from the phase detector in Figure 5 represents the spectrum and relative amplitude of jitter in the frequency domain. Examining the spectrum with a low-frequency or FFT analyzer provides the most intuitive picture of clock jitter in terms of spectrum. By integrating the signal-jitter spectrum over the frequency of interest, you can derive the rms jitter of the clock. This method is the most accurate and, unfortunately, the most cumbersome for characterizing jitter, requiring specialized test equipment (see sidebar "Integrate phase noise to derive an equivalent jitter number"). Various methods generate high-frequency clocks, and performance can vary significantly based on the technique. At less than 20 MHz, direct crystal frequency generation is sufficient for all but the most critical requirements. Low-noise options are important for you to consider for low-jitter applications for 20 MHz and greater. You can use Table 2, as well as variations and combinations of the tabulated methods, as a starting point to select a cost-effective clock-generation method. Although it is impossible to address all possible variations, some general recommendations based on years of oscillator manufacturing are helpful. Although not a complete survey of all applications, Table 3 is a starting point for specifying oscillator performance. Jitter higher than 1 kHz is considered high-frequency jitter. References
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| Author's biography Joseph Adler is senior project engineer for R&D at Vectron International (Norwalk, CT), where he has worked for 11 years. In his current position, he develops frequency-control products and core technologies. He enjoys camping; fishing; and spending time with his wife, daughter, and son. |
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