Software provides three-priority-level interrupt for 8051
Deng Yong, Department of Instrumentation Engineering, Shanghai Jiaotong University, Shanghai, China -- EDN, September 14, 2000
By using a pseudo-RETI instruction, the program in Listing 1 provides an 8051 µC with a three-level-priority interrupt system. Among the three interrupt sources in the listing, External Request 0 (INT0) has the highest priority, and Internal Time/Counter 0 (IT0) has the lowest priority. The IT0 interrupt-service routine, before the pseudo-RETI instruction, pushes the address of the first instruction behind the pseudo-RETI instruction onto the stack. The code clears the internal nonaddressable flip-flop of IT0 to acknowledge a higher interrupt after the pseudo-RETI instruction executes, and the IT0 interrupt-service routine continuously executes until the RETI instruction.
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