In-circuit testing eases design effort
Designers are employing innovative testing techniques to check shorts, defective solders, and other manufacturing problems.
Sol L Black, Lucent Technologies -- EDN, April 27, 2000
The most common way of testing the correct assembly of pc cards in manufacturing for at least the past 15 years has been in-circuit testing. In-circuit testing uses fixtures that contact virtually every net of a circuit on a card, making it easy to check for manufacturing defects, such as shorts, defective solders, and misoriented parts. But obtaining physical access to all the nets on a card is becoming increasingly difficult because of declining available real estate on the card itself, finer pitched components, and more functions per card. The outstanding advantage of in-circuit testing—access to each net—has become its major disadvantage.
Fortunately for circuit designers, advances in test technology have provided some solutions. These advances include innovative ways, such as boundary-scan testing, to eliminate test points; better ways to access small points using more rugged probes; more functional testing capability in the automated test equipment (ATE) itself; and software innovations to allow testing a part through another part. Designers are also using other test technologies that don't involve contacting the board at all, along with in-circuit testing, to provide fault coverage when holes exist in the in-circuit test. These techniques include various forms of X-ray and automatic optical inspection. Let's take a look at each of these technologies to see how it can help alleviate the pressure on circuit designers to provide more easily testable designs.
Boundary scan
The most promising solution to the net-access problem at in-circuit test is the use of the IEEE 1149.1 JTAG standard for limited-access, or boundary-scan, testing, which uses registers placed around the "boundary" of the core circuitry of each IC (Figure 1). A state machine on each package controls the boundary registers. You can, in normal operation, wire together serial ports on each package and test the entire board using a long chain of data. Tests can include checking the connections between devices as well as locating any shorts between nets even if there is no physical access to these nets. If you can drop physical access from some nets, then you can free up board real estate for more circuitry and easier routing (Figure 2). In practice and in theory, this technique often works well. But several problems emerge when you use the technique during in-circuit testing.
The boundary-scan standard targets use on a circuit with both boundary-scan and non-boundary-scan parts. In theory, you can find many defects in such mixed circuits, but you find the most defects if all parts on the card are boundary-scan components. Unfortunately, most of the digital devices on cards today are not boundary-scan components. Even parts that a manufacturer claims are boundary-scan components are often incompatible with the standard. And designers are only now considering using analog devices for use with boundary scan. In some cases, boundary-scan devices do not exactly meet the standards and therefore do not perform well with the ATE manufacturer's scan diagnostics. In other cases, the boundary-scan-description language (BSDL) that comes with the part is incorrect, which also causes diagnostic errors in the ATE software. In still other cases, the type of register, or boundary-scan cell, on a device does not allow full diagnostics using the scan software. The net result of all these issues is that boundary-scan software often does not work as well as anticipated unless the circuit has full physical-node access.
Another, more subtle issue exists when you use boundary scan on an in-circuit test set. The numerous long wires that connect to the test points of the in-circuit fixture can seriously deteriorate the signals that the board under test receives. This problem causes the incorrect diagnosis of faults and makes prove-in of the test difficult.
This problem does not mean that boundary scan is ineffective, however. When you use it in a non-in-circuit test, the signal-degradation issue disappears, although the other issues still exist. And you can test and easily diagnose a properly designed circuit on an in-circuit test set. Furthermore, you can easily test a properly designed board without physical access to as much as 90% of the nodes. Such a design greatly alleviates a designer's job by freeing up board real estate and by making bound routing easier.
From a designer's viewpoint, then, if a circuit comprises almost all-boundary-scan components, the BSDL is correct, and proper cells are on the chips, then you can remove most if not all physical access from the board. Normally, however, only a few scan parts are on the board, and the cells on the devices are not the best for diagnostics. Boundary scan is an asset even in these cases and even when boards have full access to every node, because, as devices contain more and more functions, it becomes increasingly difficult to write concise and complete tests for any given device. In fact, it is often difficult to write any tests at all. If the device is boundary-scan-equipped, however, it is easy to generate a test containing ID code; bypass; and possibly even external test (EXTEST), a test that ensures a good connection from the part to the rest of the circuitry using boundary-scan techniques. These components are sufficient to test whether a device is the correct one, is alive, and is oriented correctly. In some cases, it also tests that the leads are soldered correctly. This test doesn't help with real-estate and routing problems but does ensure electrical testing on devices that may not have had any at all. However, the situation usually falls somewhere between these two extremes, meaning that you can eliminate at least some physical test points (Figure 3).
Capacitance test of solder connections
In the last few years, designers have developed a technique for easily checking the solder connections to devices on a card, and you can use this technique during in-circuit testing. This technique uses a probe that you place on or near the top of the device under test as one plate of a capacitor (Figure 4). The lead frame of the device provides the other plate of a capacitor. A small signal is injected in one lead of the IC while the other leads are grounded (Figure 5). A sensor on the top plate then measures the signal coming through the device "capacitor" using the chip package as the dielectric. This capacitance is virtually nonexistent if there is an open solder connection to the lead. If a valid connection exists, however, the capacitance is approximately 20 fF. You repeat this process for each lead of the device.
The technique has proved effective in testing the connections to devices. It has even been successful enough to eliminate the need for performing EXTEST using boundary scan if you have full physical access to a device. The technique does have some limitations. For example, you cannot test power and ground leads in this way. Also, if you have no physical access, you cannot use the technique.
Designers like this test method because it ensures that devices are soldered correctly on the board even when there is no true electrical test or even a boundary-scan test. However, the more advanced in-circuit testers have some tricks that allow you to test the connections using capacitance techniques even without physical access to all the nodes. In some cases, for example, you can perform the test through resistors and other components in the circuit (Figure 6). When this approach is possible, you can eliminate access to some nodes. The test not only checks the solder connections on the device but also ensures that the series component is soldered properly. It does not, however, test the value of the component. To somewhat ensure that the values of these series components are correct, you should try to provide access to both sides of one of the components of each standard type in the circuit so that you can test its value. The most common reason for failure due to wrong component values is using the wrong reel in the placement machine, and testing a sample part catches this mistake.
Voltage-difference testing
An alternative technique applies a voltage to one pin of the device and another voltage to a second pin. (Figure 7). This technique measures the current drawn or sourced through one lead. It then changes the second voltage to 0V or some other value and monitors the current change. If the change is significant, then the connection to both leads is considered good. You repeat this process for all leads of the device. This process is less consistent than the capacitance technique but does test the power and ground connections. You can also use it for parts, such as those without lead frames or grounded cases, that cannot be capacitance tested. Again, you might be able to use advanced ATE to test these parts even when you don't have full access. The same relaxing of the access rule exists for this method as for the capacitance system.
Analog cluster testing
Boundary scan and advanced capacitance and voltage difference solder connection testing can help you eliminate the necessity for test access in many places on a board, but designers are increasingly using analog components on today's circuit cards primarily because the components include more and more RF circuitry. Fortunately, there is help here, too. If you can simulate an analog circuit, then, in some cases, you can drop some test points. If the ATE software is capable, then it can predict what resistance and reactance measurements are on a good board and what they are when various faults occur. If the software can make these predictions, then clear and accurate error messages will be generated that will pinpoint the faults. This method is called analog cluster testing. Most in-circuit equipment is capable of performing these cluster tests, but, in the past you had to manually create these clusters and their fault messages. Manual generation is a time-consuming and often inaccurate task. The introduction of software to automatically perform these functions is a large step forward in the elimination of some test points.
Get physical
All these ideas have discussed ways to eliminate physical access to a circuit, but you still need physical access for most in-circuit testing. Just a few years ago, designers considered test probes on 100-mil centers as dense as they could reliably use. Mechanical engineers have given much effort to better test probes. Today, the newer design-test probes are not only more rugged but also more accurate. Test points on 75-mil centers can easily provide good and dependable operation. Test points that you can use on even smaller centers are available, but questions remain about their dependability and ruggedness. The 75-mil test points can provide greater area on the pc board, thus relieving design pressure to provide spacing for larger probes.
Some boards are so dense that they have insufficient real estate for even minimal test points. If you cannot contact the board, then in-circuit testing is useless. However, techniques are available to ensure that the board is manufactured correctly. These techniques include automatic optical inspection (AOI) and X-ray inspection.
AOI uses a digital camera to compare the board under test with data from files. Basically, this technique is the same as visually observing the board for defects. The advantage of AOI is that, unlike a human observer, who cannot catch a significant percentage of defects, a machine can. However, AOI can find only visual faults, cannot verify device operation, and—more important—cannot find solder crosses unless they are directly visible.
The most accepted form of X-ray inspection is X-ray laminography, which inspects the board under test in layers. (Figure 8). It automatically looks for shorts and opens and can find these conditions even under BGAs. The computer algorithms locate and list defects, much as an in-circuit machine does. The advantage of this system is that it finds even those faults that are not visually identifiable. This technique also has the advantage of requiring no test fixture. But in-circuit testing still is necessary to determine whether the parts on the board under test are correct and are operational. In-circuit testing remains the most reliable and accurate way to isolate faults on a defective board. Test engineers see X-ray techniques more as supplements to in-circuit testing than a replacement.
A combination of techniques
Designers will for now combine all these techniques. But ATE vendors are now developing software to determine during the design stage of the pc card the test techniques that are best for each circuit. Once the software identifies these techniques, it will begin to identify which, if any, nodes you can eliminate and the potential fault-coverage consequences. This development will help both electrical and physical designers' ability to work with the test engineer to free up real estate and maintain excellent fault coverage. Preliminary versions of this important software already exist.
You can now do some of this work manually. Designers are always encouraged to discuss these techniques with their test engineers. The bottom line is that electrical and physical designers should work closely with in-circuit test engineers to determine the options for reducing and eliminating the board real estate used for test points.
Author info
Sol L Black is a member of the technical staff at Lucent Technologies (Columbus, OH), where he has worked for 37 years. In his current position, he develops in-circuit tests for circuit cards and designs for testability reviews for in-circuit tests for cellular-telephone base stations. He received an EE degree from the College of Applied Science at the University of Cincinnati. He is a senior member of the IEEE and a railroad fan.
ACKNOWLEDGMENT
Thanks to the Manufacturing Test Division of Agilent Technologies for allowing use of many of the figures in this article.
