Spice provides signal-integrity clues for high-speed systems
As you raise the clock rate-and thus the signal rise and fall times-to squeeze more performance from a design, understanding the effects of termination schemes is more important than ever. Easy-to-use PC-based Spice tools provide useful insight into the behavior of termination schemes in high-speed interconnects.
Ken Boorom, Hewlett-Packard Co -- EDN, February 18, 1999
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 Many engineers use a trial-and-error approach to fix transmission-line problems in high-speed digital circuits. They experiment on the same interconnecting trace with series termination, parallel ac termination, and sometimes both. There is a better way. Spice tools allow you to perform simple simulations with various termination and bus topologies. The simulations work equally well at 10 MHz or 10 GHz, and they don't need exotic high-frequency test fixtures. The simulation results can provide you with a seat-of-the-pants understanding of the behavior of a high-speed digital bus. For exotic and critical applications for which you can justify the training and purchase costs, more complex signal-integrity tools are available. However, Spice can provide lots of insight with little investment. Most Spice vendors offer free evaluation versions and training time.
PSpice from Orcad Inc (www.orcad.com) lets you build circuits with a graphical user interface so that you don't have to memorize Spice syntax. PSpice also has a built-in waveform-graphing function. The interface allows you to perform "what-if" scenarios, varying circuit parameters to understand how these parameters affect the circuit's behavior. This ability can provide you with an important qualitative understanding of a circuit's behavior. You can use Spice to model a high-speed digital bus by first drawing its equivalent circuit (Figure 1). The circuit in Figure 1a can model any one of the digital interconnects in Figure 1b. The circuit includes the driver voltage and rise time (VSRC), the source impedance (RSRC), any series impedance you add to match the driver's impedance to the transmission line (RSERIES), the transmission line, and any terminating capacitance and resistance you add to terminate the line (CTERMand RTERM). You can perform experiments by varying the values of the components. Using a tool such as Spice to perform these experiments before board layout can reduce project costs and lead times. Table 1 shows the parameters you need to know to model the circuit. For simplicity, examine a logic signal as it switches from a low level to a high level. The analysis and conclusion of the high-to-low case would be identical if you turn the resultant graphs upside-down. You can compare several termination schemes by varying the values of RSERIES, CTERM, and RTERM (Table 2). If your Spice tool does not accept zero or infinite as a component value, you can substitute a suitably large or small number. After you enter these values, you can perform a PSpice simulation with a single mouse click. Figure 2 shows the voltage levels at a device close to the driver. Series termination is the winner here, producing the fastest rise time with the least overshoot. The unterminated line shows the most overshoot, and both of the lines that use parallel ac termination require a longer settling time for the series capacitor to charge. At high speeds, the location of a device on a transmission line can influence both the timing and the shape of the transient switching waveform at its inputs. Figure 3 shows the voltages that appear at the end of the transmission line. In these cases, the range of the voltages exceeds that of the voltages in Figure 2. Also, the overshoot for the unterminated transmission line is more severe at the end of the transmission line. Model ground bounce A Spice simulation can also measure the driver current. Driver current is important because rapid changes in the current cause ground bounce. Ground bounce happens when a high-frequency current must sink to ground through a finite inductance, such as a bond wire or packaging lead. Ground bounce is most pronounced on falling transitions because the digital circuit must sink current to ground to discharge the interconnecting trace and its loads. On rising edges, the voltage source sees most of the noise. Ground bounce is more serious than power-supply bounce because logic circuits reference ground. Therefore, changes in the ground can change the perceived value of a logic signal. If this change causes the system to perceive high logic levels as low logic levels, spurious clocking and other problems can occur. Figure 4 shows the driver current for the various termination schemes; a positive value in the graph represents a current that would flow into the ground plane. The figure shows currents for one driver only; the effects are even more pronounced when simultaneously driving eight or 32 signals. Although a series termination improves switching waveforms and reduces ground bounce, parallel ac termination also helps with ground bounce. Specifically, these termination schemes reduce the height and slope of the current spike. Figure 4 also shows that the unterminated line alternately dumps current onto the ground and requires positive VCC current during switching. Perform a Fourier analysis The high-frequency components of the driver current are of the greatest concern because the inductive impedance of the ground path increases linearly with frequency. Spice includes a Fourier-analysis feature that shows the frequency components of the signals listed above (Figure 5). Not the highest value but the weighted product of the magnitude and the frequency is relevant here. Series termination comes out a clear winner in Figure 5. Parallel ac termination shifts the no-termination spectra to a lower frequency but does not diminish its magnitude. Click here to download the Spice listings for this article. References
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| Author's biography Ken Boorom works for Hewlett-Packard Co's Laserjet Solutions Group in Boise, ID, where he is responsible for ASIC and circuit-board qualification. He holds a BSEE and an MSEE from Stanford University (Palo Alto, CA). |
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