Leading Edge
-- EDN, January 21, 1999
|
|
 Triple ADC with on-chip PLL carries analog RGB over to flat-panel worldBy Bill Schweber The AD9884 from Analog Devices (Picture) makes it easier to use your analog RGB video signals with flat-panel displays—a task that involves considerable mixed-signal processing and support functions. The device incorporates a trio of high-speed, wideband, 8-bit A/D converters plus an input buffer, a pixel clock, and related circuits in a 128-lead PQFP device. The IC has a 140M-sample/sec encoding rate with a 500-MHz full-power bandwidth, commensurate with displays of 1280X1024-pixel resolution using a 75-Hz refresh rate. The PLL within the AD9884 develops a pixel clock over a 20- to 140-MHz range with less than 500-psec p-p jitter from a horizontal sync input of 30 to 90 kHz. You can disable the PLL to use an external clock signal if you prefer. An internal 1.25V reference, programmable gain, and clamp circuitry further reduce the need to provide peripheral functions. You program this $25 (10,000) CMOS IC via a two-wire serial bus, and you can also get a slower, 100M-sample/sec version for $20. Analog Devices Inc, Norwood, MA. 1-781-937-1428, fax 1-781-821-4273, www.analog.com . Flash drive stores 160 Mbytes in 1.3-in. package Flash-disk provider M-Systems has added support for an even smaller form factor to its ATA-based product family. The Model IDE 1.3-in. products matches the 1.3-in. form factor that Hewlett-Packard (www.hp.com) pioneered and abandoned with its Kittyhawk magnetic disk drive. Available in capacities of 4 to 160 Mbytes, the drives target handheld and ultraportable systems. You can specify the products in standard (0 to 70°C), enhanced (–25 to +75°C), and extended (–40 to +85°C) versions. A standard 160-Mbyte product sells for $440 (OEM), and the company offers the same capacity in a 1.8-in. package for $427.—by Maury Wright
M-Systems, Newark, CA. 1-510-413-5950, www.m-sys.com . Analog front end for ADSL extends linearity and local-loop length Whereas many asymmetrical digital-subscriber-line (ADSL) front ends have specifications that suit loops 12,000 to 16,000 ft from the central office, this distance covers only 60% of US residents. In contrast, Datapath’s DSP8000 analog front end offers high linearity and low noise, providing an 18,000-ft loop covering more than 95% of residents (Figure). The DSP8000 (for remote-terminal end users) and similar DSP8001 (for central-office sites) sport 14-bit linearity from 4.416M-sample/sec A/D and D/A converters, plus a receiving noise floor of –150 dBm/Hz above 300 kHz. The ICs comply with the ADSL T1E1.413 standard, yielding 8 Mbps downstream and 800 kbps upstream on short lines and 1.5 Mbps bidirectionally on longer loops. Each 128-pin PQFP IC requires four external precision resistors plus a few bypass/decoupling capacitors, as well as standard plain-old-telephone-system "reject" filtering and high-voltage line drivers and receivers. Within the 5V devices are fourth-order lowpass filters for the transmitting and receiving paths with 5% cutoff-frequency accuracy, programmable attenuation and gain for each path, and a 12-bit DAC for the voltage-controlled crystal oscillator. You configure the analog front ends via a four-wire serial port; power consumption is 675 mW in frequency-division mode and 825 mW with full echo-cancellation operation enabled. The DSP8000 and DSP8001 cost $22.50 (100) each.—by Bill Schweber Datapath Systems Inc, Los Gatos, CA. 1-408-366-1766, fax 1-408-366-1955, www.datapathsystems.com .
Fast FPGAs focus on PCI DynaChip has made several tweaks to its year-old DL6000 architecture, and the end result is the DY6000 family (see "Budding FPGAs beat last year’s crop," EDN, March 26, 1998, pg 18). Each logic block now contains an 8-to-1 multiplexer; 16-input AND-OR logic;arithmetic logic that can, for example, implement a 2-bit adder or seven-input XOR function; and dual flip-flops. You can now drive each synchronous port of the 32-bit dual-port RAM in each logic block with a different clock as fast as 125 MHz. Speaking of megahertz, the two on-chip analog PLLs, which operate as fast as 205 MHz, can not only divide and multiply an input clock, but also enable you to insert programmable latency from –4 to +2 nsec. DynaChip made many of these enhancements with PCI and other high-performance interfaces in mind. The company claims that its 64-bit firm core runs zero-wait-state PCI as fast as 66 MHz, consuming one-third of the largest device in the DY6000 family and leaving approximately 36,000 gates for other functions. The 55,000-gate DY6055, now in production, offers 1600 logic blocks; 51,200 bits of RAM; 3840 flip-flops, including I/O registers; and 320 I/O signals. It costs $174 (1000) in 240-pin QFPs or $229 (1000) in 432-bump BGAs. The DY6009, DY6020, and DY6035 are available for sampling. The company’s DynaTool back-end place-and-route software also supports the DY6000 family.—by Brian Dipert DynaChip Corp, Sunnyvale, CA. 1-408-481-3100, fax 1-408-481-3136, www.dyna.com .
Digitally dim your LCD backlight over 100-to-1 range Cold-cathode-fluorescent lamps (CCFLs) find extensive use in backlighting LCD monitors but require complex drive circuitry. Avoiding that complexity, the LX1686 from Linfinity Microelectronics implements a new architecture for the drive circuitry. The architecture eliminates some external passive reactance components, allows you to use a smaller step-up transformer, and yields a wide brightness-adjustment ratio. The 24-pin IC includes dual 100-mA drive outputs that can connect directly to FETs or bipolar transistors. Within the IC, the fixed-frequency PWM control circuit has two feedback loops—one to regulate lamp current and the other to regulate open-circuit, or "strike," voltage amplitude. The LX1686 provides and automatically monitors the special start-up voltage sequence that CCFLs require. The device also controls both its output current burst to minimize overshoot, which shortens lamp life, and its output pulse jitter, which can cause flicker from beat frequencies. The IC costs $3.30 (1000).—by Bill Schweber Linfinity Microelectronics Inc, Garden Grove, CA. 1-714-372-8335, fax 1-714-372-3566, www.linfinity.com .
Bigger+smaller MOSFET switches cut parts and design overkill In cost-sensitive designs—and which rare ones these days aren’t?—any overdesign or the need for small external components can add expense to your bill of materials. Recognizing this fact, two MOSFET vendors offer entries with functions tailored to an application’s precise needs. From Vishay Siliconix, the PWM-optimized Si4824DY IC (Picture) has asymmetric, dual, 30V n-channel MOSFETs in a single SO-8 package. One MOSFET is a 17.5-m  device, and the other is a 40-m device; together, the MOSFETs work well in synchronous-buck dc/dc-converter designs with optimal on-resistances for both the switching and the synchronous portions of the design. Gate charges for the MOSFETs are just 12 and 31 nC, adding to the efficiency of the 63-cent (100,000) devices.Along the same application-optimized concept, the FDC6325L from Fairchild Semiconductor (Picture) combines a low-on-resistance p-channel MOSFET with a smaller n-channel MOSFET driver in a six-pin SOT package. The company designed this integrated load switch for high-side power switching. It lets you drive the p-channel device directly from low-voltage logic circuits, eliminating the need for an external level-shifting transistor. Operating from battery voltages of 2.5 to 8V, the FDC6325L has 130 and 180 m maximum on-resistance at 5 and 2.5V, respectively, and can switch continuous loads as high as 1.8A (5A pk). A similar device, the FDC6326L, handles 3 to 20V loads but with on-resistance values of 125 m at 12V and 200 m at 5V. The devices cost 49 cents (1000) each.—by Bill SchweberVishay Siliconix Inc, Santa Clara, CA. 1-408-567-8220, fax 1-408-567-8995, www.siliconix.com . Fairchild Semiconductor Corp, Sunnyvale, CA. 1-408-822-2000, fax 1-972-910-8039, www.fairchildsemi.com .
Low-cost tools ease µC-based system design The PSDsoft tool suite from WSImakes life a little easier for designers of support chips for µCs. WSI developed the tools for use with its PSD chips, which integrate programmable logic, in- system-programmable (ISP) flash, EEPROM or EPROM, SRAM, I/O, and programmable functions on one chip. The $89 Windows-based PSDsoft simplifies adding external logic and memory to µC-based systems. PSDsoft supports HDL-based logic design, simulation of PSD-chip CPLD functions, µC-interface configuration, memory mapping, and programmable-function configuration on PSD chips. It also automatically generates C code for implementing ISP functions. The tool suite comes with templates for bus-interface configuration for many µCs, including the 68HC11, 8031, 80196, and 3150. PSD chips contain all required logic for the interface, which means you need no additional chips. Device-configuration options include bus width, multiplexed or nonmultiplexed operation, and µC bus-control settings for most popular 8- and 16-bit µC buses. PSDabel, WSI’s version of the Abel PLD programming language, lets you do your PSD logic design using Boolean equations, truth tables, and state diagrams. An optimizer automatically reduces logic by eliminating redundancy and maximizing resources. When you finish configuring your device, logic design, and µC firmware, PSDsoft helps you merge these results and map them to a target PSD. Finally, PSDsoft generates PSD-macrocell-usage reports along with a pinout diagram for next-level board design.—by Jim Lipman WSI, Fremont, CA. 1-510-656-5400, fax 1-510-657-5916, www.wsipsd.com . Voodoo offers new features for believers, trade-offs for skeptics The Voodoo3 architecture from 3Dfx Interactive continues the single-chip-integration trend the company began with its Voodoo Banshee (see "Hot summer delivers scorching graphics," EDN, Oct 22, 1998, pg 16). The Voodoo3 family, currently comprising two devices, offers substantial functional and performance improvements over Voodoo2-based chips. However, 3Dfx made some surprising feature-set trade-offs to achieve these goals. Voodoo3 contains both 2- and 3-D graphics cores, plus hardware assistance for digital-versatile-disk decoding. Unlike Voodoo Banshee, the 3-D core offers the same dual texture-rendering pipelines and single-cycle, single-pass multitexturing capability as the 3-D-only Voodoo2. The company has also cranked up the performance, claiming more than 7 million-triangle/sec rendering for the high-end, $45 (10,000) Voodoo3-300. The device also offers a 366-megatexel/sec fill rate, a 350-MHz RAMDAC capable of 2048X1536-pixel resolution at 75-Hz refresh, and a 183-MHz core operating frequency. These capabilities exceed those of the current 3-D performance leader: two Voodoo2 chips operating in a scan-line-interleave mode. Corresponding specifications for the $35 (10,000) Voodoo3-200 include 4 million-triangle/sec rendering, a 250-megatexel/sec fill rate, a 300-MHz RAMDAC capable of 2048X1536-pixel resolution at 65-Hz refresh, and a 125-MHz core operating frequency. Both chips include a 2X Advanced Graphics Port (AGP) sideband interface (with 4X AGP support planned for this year), a video-module-interface port, and direct connection to 3Dfx’s optional LCDfx flat-panel-display-driver chip. According to 3Dfx, both chips are available for sampling and will enter volume production in the second quarter. So what’s not to like about Voodoo3? First, the chips support only a maximum 16-Mbyte frame-buffer size, a curious limitation in this era of cheap DRAM and constantly growing game texture-map sizes. The company based Voodoo3 on its Voodoo2 3-D core (which itself is a minor derivative of the original Voodoo architecture). This decision undoubtedly let 3Dfx quickly get Voodoo3 to market, but it also means that the chips don’t output 24-bit color and support only 16-bit Z-buffer precision. Both factors reduce image quality, and, although these trade-offs may make the chips faster, why do the devices need to render new frames at rates that far exceed most viewers’ ability to perceive them? Although image quality is perhaps a secondary consideration in today’s shoot-’em-up games, it will become much more important as 3-D expands into other PC applications.—by Brian Dipert 3Dfx Interactive Inc, San Jose, CA. 1-408-935-4400, fax 1-408-262-8874, www.3dfx.com .
All-in-one chip set makes digital cameras a snap Sierra Imaging’s Raptor II makes key improvements on the first-generation chip set that Epson (www.epson.com) and other camera manufacturers use. Raptor II includes two chips; one contains an image processor and 32-bit ARC Cores (www.arccores.com) RISC CPU with a separate 8-bit microcontroller handling system functions. Raptor II directly interfaces to Universal Serial Bus; iRDA; RS-232C; NTSC and PAL video, including S-Video; ATA; LCD; and as many as three motors. Add memory, a lens, an image sensor, and a display, and your hardware design is complete. The company optimized Raptor’s II architecture for CMOS and CCD sensors as large as 8 million pixels, but the chip set interfaces to those as large as 16 million pixels. Although camera users might like high-resolution pictures, they expect continued reduction in picture-to-picture delays. Raptor II responds with performance 10 times faster than its predecessor, outputting fully processed JPEG images as fast as 3.3 million pixels/sec or displaying 320X240-pixel video images at 30 frames/sec. Sierra Imaging also focuses on extending battery life; Raptor II runs at 2.5V with 3.3V I/O signals and offers extensive system-power-down-control facilities. The company’s next consideration was software support. The real-time Sierra system-software platform requires 300 kbytes of memory. Sierra Imaging also offers a fully functional reference-design kit with documentation and customization suggestions. Chip-set sampling ($100) will begin in April, and the company schedules volume production ($20) for July.—by Brian Dipert Sierra Imaging, Scotts Valley, CA. 1-408-461-2070, fax 1-408-461-2072, www.sierraimaging.com .
Mezzanine modules speed VME data transfers Real-time radar, high-frequency sonar, image-processing, and transient-capture systems based on the VMEbus use auxiliary high-speed datapaths to transfer data between multiple processors and superfast I/O peripherals. These datapaths offload VME’s limited backplane-bus data rates to extend the overall bandwidth of the application. Overcoming the data-rate limits, two new plug-in mezzanine modules from Pentek (Picture) allow you to select a standard bus-bypass technique that matches your system. The model 6220 velocity-interface-module mezzanine board attaches directly to the company’s DSP boards to provide a single-slot, high-speed Raceway interface. Mercury Computers (www.mc.com) developed the high-speed Raceway synchronous-backplane fabric, which operates independently of the VMEbus and provides multiple, simultaneous, 160-Mbyte/sec data channels between boards. Another new mezzanine module, the model 6226, supports the Front Panel Data Port (FPDP) standard for a front-panel-ribbon-cable interface based on a 32-bit parallel communication link that delivers data at 160 Mbytes/ sec. Pentek’s quad-DSP board accommodates two FPDP modules to give one bidirectional data-port per processor. Prices for the models 6220 and 6226 start at $2000 and $995, respectively. Both modules will be available in the second quarter.—by Warren Webb Pentek Inc, Upper Saddle River, NJ. 1-201-818-5900, fax 1-201-818-5904, www.pentek.com .
|
on-resistance and 45-msec overcurrent-response time. The eight-pin SOIC/ DIP and 14-pin TSSOP switches handle continuous currents from 0.3 to 3A, depending on model, and cost $1.01 to $1.11 (1000).—by Bill SchweberTalkback
