Leading Edge - Europe
-- EDN, January 7, 1999
 Digital-phosphor scopes aim to finally oust analogueby Graham Prophet With Tektronix’s TDS3000 family ( Picture) of digital phosphor oscilloscopes (DPOs), you can control waveform displays with many of the look-and-feel characteristics that have made many people hang onto their analogue instruments while using advanced analysis capabilities. Tek introduced the DPO technology several months ago and is now putting it in a series of instruments with prices of £2035 to £6920. The devices range from a two-channel, 100-MHz, 1.25G-sample/sec unit to a four-channel, 500-MHz, 5G-sample/sec device. DPO technology uses intensity modulation of the waveform display, in addition to colour, to represent information about the frequency of occurrence of events in a waveform. This approach gives you both the control over the display that comes with a DSO and the extra dimension of interpretation that an analogue unit used to give you. Physical format is the "lunch-box" shape that first appeared on Tek’s TDS200 series. Signal processing occurs parallel to the signal path from acquisition to screen, rather than within that stream, an architecture that Tek claims minimises the dead time—when no data is acquired—of a traditional scope. Tektronix, Marlow, UK. +44 1628 403300, www.tektronix.com.
ASIC emulation targets next-generation portable-phone designs Despite the commercial upheavals in the ASIC-emulation market (still in a state of flux at press time), two companies in the sector have introduced new products. Mentor Graphics’ Meta Systems Division has built the Super-C, its biggest ever version of its Celaro. Super-C has slots for 192 of its proprietary-architecture configurable processor boards. With the resources of a Super-C, you could emulate as many as 26 million gates with compilation rates of 2 million to 3 million gates per hour. You could, that is, if you had the only one of this size yet built, a $6 million machine, believed to be destined for a major Japanese ASIC manufacturer. At a smaller scale, Meta plans to provide a more basic 48-slot machine to UK-based Pixelfusion ( www.pixelfusion.com) as evidence that the technology is viable even for a start-up. Pixelfusion is using the technology to verify its 50 million-transistor image-processing chip, due out next year. Meta also says it is investigating options for time-based access to its large machines. Designed with a different philosophy in mind, Aptix’s MP3C ( Picture) helps you design systems such as third-generation wireless ASICs, with support for DSP and pipelined structures. Based on Aptix’s field-programmable interconnect technology, which the company now uses exclusively for its emulator products, the MP3C can handle as many as 12 modules, equating to about 600,000 gates per board. Emulations run at 10 to 30 MHz; the Aptix architecture gives you access to hardware probing of all nodes of the emulated design. The company’s design philosophy is to use a block-based approach, verifying a new design incrementally; if you are operating in a concurrent design environment, you can use this approach in parallel with block design. This approach stipulates that you work with the hierarchy in the design without flattening netlists. The new AggreGater tool provides the link from system-level Verilog, EDIF, or XNF netlists to the Aptix hardware, once again focusing on managing the hierarchy and moving the design from one environment to the other in a block-structured manner. You can link verified components, such as imported cores, as black boxes.—by Graham Prophet Mentor Graphics, Meta Systems Division, Les Ulis, France. +33 1 64 86 61 00, www.mentorg.com. Reconfigurable analogue ICs reach wider applications Fast Analog Solutions adds the TRAC020LH to its Trac family of field-programmable analogue devices, offering improved bandwidth and lower power consumption and power demand over previous devices. You can in minutes implement an analogue function directly from the signal-processing algorithm level to hardware. The company subdivides the chips into "cells," blocks that perform analogue signal primitives. You can configure and combine these cells to define functions. The device has 20 such cells, and a basic function that the company calls "noninverting pass" now runs at 12 MHz—three times the previous rating. This function typifies the increase in bandwidth. Accuracy is now an order of magnitude better than the earlier generation parts, and power demand is lower by a factor of four to 5 mA per chip with a 10-µA standby mode. The company offers a custom target development board and Windows-based programming-simulation software. You can programme the chips from either EEPROM or a µP bus in a similar way to logic FPGAs, and you can cascade chips for complex functions.—by Graham Prophet Fast Analog Solutions, Oldham, UK. +44 161 622 4567, www.fas.co.uk. Single mixed-signal simulator draws closer You can look forward to a single-kernel simulator that will handle both logic and linear structures, based on a prototype that Analogy recently delivered to the US Department of Defense. Based on the analogue extensions of VHDL, now being ratified (IEEE 1076.1, VHDL-AMS), the simulator is a step in Analogy’s planned route to TheHDL, a single, commercial, open-simulation environment. The prototype runs VHDL-AMS and draws heavily on tools such as the SabreScope postprocessing-engine and waveform-analysis tool. Evaluators have tested it using mixed-signal blocks, such as PLLs, with favourable results, Analogy says. The company plans to publish the specification for TheHDL and to make it completely open. The company anticipates that adoption of the analogue version of VHDL (and of Verilog) will require an education effort similar to the one that was required to support initial acceptance of the pure-logic versions. You can expect to see moves this year from Analogy to help that learning process get under way.—by Graham Prophet Analogy, Swindon, UK. +44 1793 432266, www.analogy.com. Multifunction SOHO terminal chip targets ATM networks With Ericsson Components’ asynchronous-transfer-mode (ATM) PBM 990 08/1 multiservice chip ( Picture), you can design a network terminal that allows domestic and small-office/home-office (SOHO) users simultaneous access to multiple telecommunication and data-communications services. The IC simultaneously supports telephone calls, digital video, and Internet access. It communicates with modem and transceiver ICs via a Utopia Level 2 interface, distributing and collecting data to and from a range of service interfaces. Overall data rates can be greater than 155 Mbps downstream and 100 Mbps upstream, so you can design for physical media, such as asymmetric digital subscriber line, very-high-bit-rate digital-subscriber line, fibre to the home (or to the kerb), and hybrid-fibre coax. Ericsson says that it has set up software commands for most common functions. The chip integrates ATM forum 25.6 and plain-old-telephone-system/integrated-services-digital-network functions and provides a pulse-code-modulation interface for as many as four 64 kbps channels or a single E1/T1 interface. Users can add other services, such as Ethernet. The device has a generic CPU interface, so you can choose any µP. Price is $27 (50,000).—by Graham Prophet Ericsson Components, Kista, Sweden. +44 1793 488300, www.ericsson.com/microe.
Die-size packaging minimises op-amp footprint You can’t get a smaller op-amp package than National Semiconductor’s LMC60351BP ( Picture). This flip-chip-mounted dual device is the same size as the bare die. By carefully choosing materials, National minimises the manufacturing steps. The company gives the top of the wafer a second passivation layer with apertures over the die’s bond pads and reflow-solders solder balls onto the pads to form flip-chip-mounting "bumps." An epoxy coat protects the back of the wafer, and the devices are sawn apart in the usual way. The result? A 1.45-mm-per-side dual op amp that meets full hermetic environmental specifications and that conventional surface-mount equipment can still handle. National plans to add other functions, such as regulators, timers, ADCs, temperature sensors, comparators, and other op amps in the same style over the next 18 months.—by Graham Prophet National Semiconductor, Furstenfeldbruck, Germany, +49 180 530 85 85, www.nsc.com. Upstream cable modem design adapts on the fly A design for an upstream cable modem incorporates Bo4 ( Picture), a new design of integrated burst receiver from the Belgian research centre IMEC and Siemens Atea ( www.siemens.be). The modem is in field trials and will be available for implementation by licensing and transfer of intellectual property. You might consider this design ( Picture) if you are implementing hybrid-fibre-coax network hardware. The upstream data link is 10 Mbps, but the path from each subscriber to the CATV head end differs, requiring different equalisation for the signal from each subscriber. The Bo4 design can adapt to the characteristics of each frame of data. The first few bits of the preamble provide sufficient information for the Bo4 to adapt the equalisation response in time to correctly recover the payload bits of the frame. Effective performance decoding the upstream burst provides a 10-Mbps data rate in a 3-MHz bandwidth, or 3 bits/Hz.—by Graham Prophet IMEC, Leuven, Belgium, +32 16 28 12 11, www.imec.be.
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