Cadence, IBM team for 32-nm SOI IP

The companies will develop DDR PHYs, memory controllers, and protocols such as PCIe and Ethernet under 32-nm SOI (silicon on insulator).

Suzanne Deffree -- EDN, May 24, 2010

EDA giant Cadence Design Systems Inc has inked a joint development agreement with IBM to create IP (intellectual property) cores for use in SOC designs.

Under the agreement, the companies will develop DDR PHYs, memory controllers, and protocols such as PCIe and Ethernet under 32-nm SOI (silicon on insulator). Cadence said the technology will be used in servers, video games, and other devices and will be available through the company's Open Integration Platform.

"The IP we're working on with Cadence will provide state of the art building blocks that will allow our customers to build more powerful, higher bandwidth networking and communications technology," said Marie Angelopoulos, director of IBM Microelectronics, in a statement today. "This collaboration with Cadence combines IBM's expertise in developing and integrating process and IP technology with Cadence's experience in IP development to supply customers with the tools needed to build a new generation of communications infrastructure."

The agreement is the latest effort in the long-running collaboration between the two companies. In 2002, Cadence and IBM established a new series of agreements that extend the licensing of Cadence EDA tools by IBM for both internal and external design projects.  Cadence has also collaborated with the IBM-lead Common Platform technology partners to develop the 65-nanometer flow.

Most recently, Cadence and IBM along with ARM supported the SOI Industry Consortium's "Ready for SOI Technology" program by making an initial offering of SOI IP.