MEMS, asynchronous logic enter SOC-design flow

Ronald Wilson, Executive Editor -- EDN, May 27, 2010

Coventor provides MEMS-creation tools popular with specialists. C-Ware, for example, is a multiphysics simulator for modeling MEMS structures, and SEMulator is a 3-D-process-simulation tool for designing process steps to create the structures. Together with a 3-D-design-entry tool, the suite allows MEMS experts to create structures, investigate their behavior, and craft a manufacturing flow for them.

The next logical step, according to Michael Jamiolkowski, Coventor's president and chief executive officer, is to create behavioral models of the structures in C++ and electrical models in an accepted SOC-design environment and drop the designs into a library as reusable, parameterized IP (intellectual property). That task is the function of Coventor's new tool, MEMS+, a complete subflow for creating MEMS elements and integrating them into Cadence's Virtuoso.

MEMS+ includes a schematic generator and modeler, managers to handle materials and process data, a 3-D viewer, and layout and DRC (design-rule-checking) tools. Using this package, MEMS experts can create a new device design, along with a schematic symbol, an electrical netlist, a parameterized cell, DRC and LVS (layout-versus-schematic) data, and behavioral and electrical models for Spectre and UltraSim.

In some ways, Tiempo's task is similar. The company's technology uses a data-encoding scheme to indicate to a receiving block when valid data arrives from the transmitting block. The approach requires an area overhead of 20 to 50% but significantly reduces both static and dynamic power; is virtually insensitive to pressure, voltage, and temperature variations; offers sharply reduced emissions; and can detect some security attacks.

Tiempo has for some time used the technology to produce IP, including a 16-bit microcontroller and a cryptoprocessor for contactless smart cards. Now, the company is offering a flow to make asynchronous design accessible to designers who don't know-and don't care to learn-the fine points of the technology. The flow begins with a transaction-level description of the desired block in SystemVerilog. Tiempo's tools synthesize the SystemVerilog code into a Verilog netlist, using a library of combinatorial and asynchronous cells. Verification is through either mixed-mode Verilog/SystemVerilog simulation or FPGA prototype.

The flow puts complex asynchronous blocks within the reach of ordinarily skilled SOC-design teams, according to Serge Maginot, Tiempo's president and chief executive officer. Designers need to learn only how to write a transaction-level model in which concurrent processes communicate through channels using read and write primitives, how to write interfaces between the asynchronous block and its synchronous surroundings, how to create timing constraints for the interface-resynchronization points, and how to create throughput constraints for the asynchronous paths.

In a way, both tool-flow announcements are signs of the times. The emphasis in integration is slowly shifting away from more gates, more memory, and more CPU cores and toward integration of new kinds of devices that haven't previously been on the die at all. The range and quality of passive components available to custom designers have been gradually increasing. Now, we are starting to see third-party tools for MEMS and for the asynchronous blocks that have long been the purview of only the largest and best-funded design teams in organizations such as Intel and IBM. More than Moore's Law is upon us.

Contact me at ronald.wilson@cancom.com.