National Semiconductor, Silicon Labs team up for power-brick reference design

Paul Rako, Technical Editor -- EDN, May 27, 2010

Silicon Laboratories and National Semiconductor have both contributed ICs to a power-brick reference design they co-developed. The brick uses a half-bridge architecture, with two FETs and two capacitors. The design targets use in networking, communications, and high-end server applications. It uses a National Semiconductor LM5035C PWM (pulse-width-modulation) controller and a Silicon Labs Si8420 isolator. The reference design produces 100W output power and comes in a 2.28×1.45×0.5-in. quarter-brick form factor. Input voltages to the brick can range from 36 to 75V, and it withstands 100V input transients. The board output is 3.3V at 30A, and efficiency is 89% at 30A and 92% at 15A output current.

Operating at a 400-kHz switching frequency, the device has a line regulation of 0.1% and load regulation of 0.2%. The six-layer design uses 2- and 3-oz copper on the outer and inner layers, respectively. It requires 200 cfm of airflow to maintain thermal integrity and offers both undervoltage lockout and overvoltage protection on the input bus. The PWM chip integrates 2A half-bridge gate drivers. The board's designers used the Silicon Labs isolator to send secondary-synchronous-rectification gate-drive signals across the isolation boundary. An LM8261 op amp drives an NEC PS2811 optocoupler to provide isolation for the feedback signal. The LM5035CEval board costs $135. The free reference-design files are available at National's Web site.

National Semiconductor

Silicon Laboratories