The time is now for 3-D stacked die
As the semiconductor industry moves from “more Moore” to “more than Moore,” 3-D-stacked-die implementations will become critical for implementing ever-denser chip packages.
Rick Nelson, Chief Editor -- EDN, July 15, 2010
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As the semiconductor industry moves from “more Moore” to
“more than Moore,” 3-D-stacked-die implementations will
become critical for implementing ever-denser chip packages.
Interest in the technology is strong, based on an overflow
crowd attending a June 16 DAC (Design Automation
Conference) panel, “3-D stacked die—now or in the future?”
The consensus seemed to be that the 3-D revolution is imminent.
Panelist LC Lu of TSMC (Taiwan Semiconductor Manufacturing Co) said
that his company is developing the TSV (through-silicon-via) technology
that will interconnect the stacked chips in stacked die, with a focus on
design, packaging, and testing—not just the fabrication process.There are obstacles, however. Panelist Myung-Soo Jang of Samsung suggested that accurate design and analysis tools that work together in a seamlessly integrated flow could speed the adoption of 3-D implementations. Lu agreed that new design methods could help address challenges related to good-die sorting, process variations, and thermal and mechanical stress.
Manufacturers are making progress on the design-tool front. Atrenta, Auto- ESL, Qualcomm, and IMEC at DAC demonstrated a working prototype front-end 3-D chip-design system. The flow the companies demonstrated addresses 3-D-aware high-level synthesis, early partitioning, floorplanning, and multidomain analysis. “The daunting challenges of 3-D design demand a 3-Daware high-level-synthesis approach,” said Atul Sharan, president and chief executive officer of AutoESL.
“Early partitioning, floorplanning, and analysis yield substantial benefits for design predictability on conventional advanced SOCs,” said Ravi Varadarajan, Atrenta fellow. “With the emergence of 3-D multitechnology design, this activity now becomes an absolute must-have. You simply cannot hand off a 3-D design to back-end implementation without knowing for certain that it’s partitioned correctly.”
The demonstration grew out of what
Riko Radojcic of Qualcomm called
PathFinding technology, which Qualcomm
has been developing over a
number of years. According to
Radojcic, with traditional
Moore’s law process migration—
from 90 to
65 nm, for example—
it’s relatively easy
to project what will
happen. The new geometry
will yield devices
that are smaller,
faster, and more prone
to leakage—information
that can assist in building
working and yielding parts.
Such projections aren’t necessarily valid or helpful with 3-D parts. Something that allows you to explore knobs at both the architectural and the process ends is necessary, said Radojcic. “That’s PathFinding to me.” The collaboration with Atrenta, Auto- ESL, and IMEC, he added, is an effort to build a commercial set of tools that assist the PathFinding function.
Pol Marchal, principal scientist for IMEC’s 3-D SOC-design initiative, who assisted with the June 14 demonstration, addressed PathFinding technology on June 8 at the IMEC Technology Forum at IMEC headquarters in Leuven, Belgium. IMEC’s overall 3-D efforts, he said, involve investigations of TSV technology, wafer thinning and back-side processing, the packaging of 3-D die stacks, cost modeling, and 3-D system exploration, with the last being germane to PathFinding technology.
Marchal called PathFinding a systematic exploration of trade-offs. “Understanding the system requirements provides the engineer with inputs to guide design and technology decisions,” he said, adding that a PathFinding flow allows engineers to iterate on design and technology choices to optimize footprint, timing, thermal performance, and other functions.
Marchal cited as an example a mobile consumer device, which would require three or four chip tiers with a package thickness of less than 0.6 mm and more than 1000 TSVs per tier operating at 400 MHz and providing a 12.8-Gbyte/ sec data rate, all while consuming less than 2.5 pJ/bit. PathFinding analysis, he said, shows the feasibility of building such a device.
Despite the emergence of 3-D-design tools, obstacles will remain to the widespread adoption of 3-D techniques. DAC panelist Joe Adam of JMA Consulting predicted that incumbents with significant investment in 2-D technologies will be reluctant to change. Ultimately, however, resistance is futile. As IMEC’s Marchal told the June 16 DAC panel attendees, “Practice today or don’t play tomorrow.”
Contact me at richard.nelson@cancom.com.
Talkback
-
Thermal is not a challenging issue in 3D-ICs
For 3D-ICs thermal issues appear when a stack is made with predefined dies.
That's true for an SiP, not for a 3D-IC integrated system.
If 3D-ICs are made from scratch from a design using design planning,
partitioning and automatic placement/routing across the 3 dimensions,
there will be a huge gain on power consumption, then on thermal dissipation.
The gain is of more than 2 orders of magnitude.
Thermal issues disappear, or at least become a non challenging problem to solve.
People talking about thermal issues with 3D-ICs are making a simple addition
of the thermal (power) dissipated by the individual tiers, considering them as they are in 2D.
That's like making buildings by stacking individual houses. That is not optimal at all.
New design paradigms and techniques have to be invented and adopted when addressing 3D-IC integration.
Kholdoun Torki - 2010-20-8 07:49:04 PDT -
Thermal is not a challenging issue in 3D-ICs
For 3D-ICs thermal issues appear when a stack is made with predefined dies.
That's true for an SiP, not for a 3D-IC integrated system.
If 3D-ICs are made from scratch from a design using design planning,
partitioning and automatic placement/routing across the 3 dimensions,
there will be a huge gain on power consumption, then on thermal dissipation.
The gain is of more than 2 orders of magnitude.
Thermal issues disappear, or at least become a non challenging problem to solve.
People talking about thermal issues with 3D-ICs are making a simple addition
of the thermal (power) dissipated by the individual tiers, considering them as they are in 2D.
That's like making buildings by stacking individual houses. That is not optimal at all.
New design paradigms and techniques have to be invented and adopted when addressing 3D-IC integration.
Kholdoun Torki - 2010-20-8 07:44:56 PDT -
There is something counterscalable about TSV's. As more are added to a chip, the chip gets bigger. I can't see the cost factor helping.
guest - 2010-30-7 22:51:49 PDT -
Thermal considerations are indeed important, on a very fundamental level. Reducing the electrical conductor length between chips automatically reduces the distance heat can travel as well along the conductor, as well as shorter distances outside the conductor. Mechanical engineers tend to remind electrical engineers about this all the time.
mechie - 2010-27-7 10:17:01 PDT -
The thermal sinking of TSVs can be some help but not enough when you have heat sources on every tier.
synopsys - 2010-26-7 03:19:50 PDT
