Tool gives early area, power, and timing estimates

Rick Nelson, Chief Editor -- EDN, July 15, 2010

Atrenta has announced the SpyGlass-Physical, which enables RTL (register-transfer-level) engineers to achieve faster design closure by modeling physical-implementation effects at the RTL stage of the design. Previous members of the SpyGlass family provide information on whether a design is syntactically correct and testable; the new member provides early estimates of area, power, timing, and routability for RTL designers who lack physical-design expertise or tools. According to Ravi Varadarajan, Atrenta fellow, the new tool does not replace a customer’s favorite implementation tools but rather makes them more efficient, allowing designers to identify problems earlier in the design cycle.

In addition, the time penalties of successive iterations using traditional tools—in which you find problems after place and route, for instance—limit the amount of exploration designers can do, with the result that they might settle for a suboptimal solution. SpyGlass-Physical alleviates that problem.

François Rémond, director of CAD at STMicroelectronics, describes his use of the SpyGlass-Physical tool in the design of a 55-nm set-top-box chip, which includes 209 million transistors, 230 clocks, 7 million placed instances, 500 signal pads, 53 RTL-IP (intellectual-property) blocks, and 160 hard-IP blocks. He explains that the timing and physical closure of such chips represent a big challenge. “We needed a tool that would partition our SOCs [systems on chips] based on our requirements and provide trade-off analysis and guidance for our implementation tools,” he says. “The SpyGlass-Physical product achieved that [goal] on 40- and 32-nm SOCs in significantly shorter time than we expected.” SpyGlass-Physical runtimes can range from two to three hours, which represents a large savings over finding problems deep in the implementation.

The product helps to achieve performance targets in concurrent block- and SOC-development processes by using a set of interactive implementation-analysis features.

The result is enhanced guidance for the implementation of both IP blocks and full-chip SOCs. SpyGlass users can easily integrate the product into their design flows and realize the benefits of early physical-implementation modeling.

“Chip-design companies have a great need to reach faster design closure than ... current flows [support],” says Ajoy Bose, PhD, chairman, president, and chief executive officer of Atrenta. “The ability to model the impact of physical implementation on the design at an early stage is a critical aspect that is missing from today’s RTL flows.

The SpyGlass-Physical product addresses this gap by providing early estimates of area, power, timing, and routing congestion.”

Atrenta