CEO on Mentor's role in IC and system design plus test

By Rick Nelson, Editor-in-Chief -- EDN, July 21, 2010

In a wide-ranging interview July 14 at Semicon West, Walden C Rhines, chairman and CEO of Mentor Graphics, addressed the challenges the EDA and semiconductor industries face as geometries shrink, EUV arrives, and ICs expand in the third dimension. He also commented on the challenges embedded-system designers face and on what Mentor is doing to help, and he described a bright future for design-for-test and built-in self-test technologies.

EDN: You delivered a keynote at last year's Semicon West in which you exploded semiconductor market myths. If you were to give a presentation this year, what topic might come to mind for this audience?

Rhines: It would be yield enhancement or resolution enhancement, or it might be 3-D challenges.

EDN: 3-D was a big topic at the Design Automation Conference a few weeks ago.

Rhines: It was. It seems like at every conference it's a big topic.

EDN: How is Mentor addressing the challenges there?

Rhines: We are working directory with customers to assure the tools we provide are available ahead of the need for whatever people do. So, of course, physical verification is one of the straightforward pieces that people look to us to set standards for, so we work with partners on what they are planning and what their sequence of rollout will be. Really today, beyond memory, most of the 3-D usage is still pseudo 2-D—that is, stacked memory with logic or memory with analog. You can treat the design as 2-D, so it really hasn't created the big challenges that we have ahead.

EDN: And what are the challenges ahead?

Rhines: Ahead, more and more we will be facing issues with parasitic extraction, timing, floor planning—all the things you have to do to put multiple die stacks together and assure they work properly. There will be an evolution of essentially the whole tool chain, at least on the physical side, and there will be some effect on the logical side to support the alternatives that now arise, because you don't know when you start what might end up on which layer. It's a more complex problem than just growing in the third dimension—you now have the delay associated with through-silicon vias, you have the parasitic effects, and you have the placement of those vias as an issue. How to address that all efficiently in a design creates some good challenges, and that's always good because that's the only way the EDA industry grows—by addressing new problems.

EDN: What do you see as a timeline for commercial tools for 3-D?

Rhines: I think it's certainly evolutionary. There are people we are supporting today with rule sets in verification that have been extended because of the need to check for things that affect die stacking, and I think at the same time people are stacking die they are also growing in the z dimension, so there are rule sets that have to support increased levels of interconnect and other features as well. So all of that is happening in an evolutionary fashion.

EDN: So there won't be one sudden point at which you say, "here is everything you need for 3-D design"?

Rhines: I don't believe so—on the EDA side I think you will see steps where all of a sudden it becomes cost-effective to start stacking a more difficult die stack. We went with die stacking and ball bonding to memory for quite some time, and then all of a sudden we saw the first introductions of TSVs on the memory die stacks. And I think a parallel thing will happen in logic. People initially will use it because it gives a capability that they can't achieve easily other ways. Then as it becomes more manufacturable the cost will come down, and so more and more it serves as a substitute for Moore's law—a way to put more functionality per unit density. If you want to know the rate at which it will occur, you can look at where you have to be on the learning curve, where the cost has to be, and you can then estimate what you think the cost of shrinking feature sizes is. Then you look at the tradeoffs and decide, is it going to be more cost-effective to stack them or more cost-effective to shrink in the x-y plane?

EDN: You mentioned yield enhancement. Are there still issues even in the 2-D chips that need to be addressed, and is that driven by process shrinking?

Rhines: It's driven by a couple of things. Manufacturing variability, of course, is a driving force that becomes a bigger percentage of impact on a design with time. But I think the big discontinuity came when an EDA company—Mentor—was able to correlate the database from test results with the database from physical layout. That enabled voluminous comparisons that showed where the failures were occurring and mapping that physically to discover systematic weak points in a design that were much too subtle to show up in failure analysis—or at least that were difficult to discover in failure analysis physically but which could be discovered in an automated fashion quite rapidly. And you could have a significant yield impact by finding these secondary systematic failures.

EDN: Will there be issues with EDA for going to EUV?

Rhines: EUV will require resolution enhancement, just as 193-nm immersion does. Depending on when you believe EUV will hit the roadmap, there is no scenario I know of where it will hit at such a time that you won't require resolution enhancement to go with it. So we have significant development activity on EUV right now in preparing for the resolution enhancement that will have be rolled out when EUV is rolled out.

EDN: Is there still more work to be done with the 193 nm?

Rhines: Yes, it's a real workhorse light source. If you look compared to other generations of lasers, we've really stretched 193 a long way and will continue to push it, and it's very clear to us that our computational lithography will be able to bear the burden of the shrink to 20 nm, so that 193 immersion will be the preferred lithography for 20 nm, as well. The issues about double etch and so on add a little complexity, but in terms of basic lithography one more generation beyond 28 looks like an assured thing.

EDN: So we can hold off on EUV until we get below that.

Rhines: You can, and of course the semiconductor industry has a strange way of making technologies go further than you would think they'll go. So we have to be prepared for moving beyond, which I think is quite possible, and that of course will require further computational lithography for resolution enhancement. Fortunately, Mentor is in a situation where we are paired with an excellent partner in IBM in doing the development, and the big impact has been in the ability to work on real designs, real processes right from the start, so that we were able to close in quickly on the key issues and move rapidly in developing the solution.

EDN: Getting back to the 3-D and the challenges there—do you consider them primarily technical, or are they business related? There was some talk at DAC that people really don't want to go there because they already have investment in 2-D.

Rhines: Well, I don't want to minimize the technical challenges with 3-D. When you get beyond memories and two-die stacks there are some very significant issues—thermal issues, EMI issues, parasitic delay issues, and so on—that require a lot of work. But I don't believe that the prior investment will ultimately be the barrier. I believe it will be the tradeoff of cost reduction of a new technology vs. extension of an old technology. Which one gives you more functionality or more transistors per dollar? So I think it will simply become apparent as we evolve these technologies what the relative cost learning curves are going to be and how much has to be overcome. And we'll make the tradeoff versus, for example, the throughput of the steppers on smaller lithographic features. As far as I know there has never been a generation of stepper that produced less silicon area per hour per capital dollar than the one before. There has always been an improvement. And continuing that is becoming a bigger challenge. And when you compare that with, "What could I do without shrinking design rules but stacking die instead and dealing with the TSV problems?"—there will be a point where stacking die becomes a favorable tradeoff.

EDN: What about power-aware design?

Rhines: It is probably the single biggest challenge of designers today. It clearly supersedes performance and density in terms of being the limiter of new designs. To me the big opportunity ahead is moving the power analysis earlier in the design phase. So up to this point we have had many years of optimizing physical layout for low power. We've had just under a decade of optimizing the actual functional features—power down, lower voltages, multiple voltages. And we fairly recently have been moving into system-level optimization where you actually optimize the whole architecture. And that's where the hot tools are, to do tradeoffs at the architectural level. Our tool is called Vista. It's actually a TLM [transaction-level modeling]-based tool. It uses SystemC to model the tradeoffs between power vs. performance at the transaction level and helps people to make architectural decisions that will lead to a low-power design. And if you look at the relative impact, system-level tradeoffs like that offer order-of-magnitude kinds of improvements compared to physical layout improvements, which are 20 to 50% kinds of improvements.

EDN: Getting away from the semiconductor area, Mentor Graphics has a raft of products for embedded systems and so forth. One thing that came out of the Design Automation Conference was the keynote address by the corporate vice president of innovation products at Motorola Mobile Devices Inc, who talked about designing the Droid phone. He said his big problem was that design tools did not let him optimize power, for example, at the end-product level. His complaint was that SOC designers will sell you a chip and say, "this is optimized," but when you put it together with other chips the power optimization falls apart. Are there prospects for addressing that?

Rhines: Yes. So system-level optimization, which involves multiple chips or board-level design is not only a big opportunity—there are tools available. First, there are power-integrity tools at the system level available, and one has actually been the fastest growing system-design tool in our history—this past year we went from zero to millions of dollars of sales in a period of about six months. So that's one piece. Another is the ability to have an embedded operating system that allows for power optimization. In fact, we have such an embedded operating system, called Nucleus, and in fact we have customers who have achieved order-of-magnitude improvements in power consumption simply by how they did things in the real-time operating system. And then lastly with respect to Android, we haven't been asleep. Even though over half the cell phones in the world today use Nucleus from Mentor we have a very active Android operating-system team that is in fact focused on things beyond cell phones, and that's become a significant business for us—implementing solutions that do the same kind of power optimization that Nucleus does. This is not far away.

EDN: What about combining mechanical and EMI simulations at the system level, as well?

Rhines: Multiphysics simulation has been a major focus for us for many years now. It's been slow growing, but it's been quite popular with the systems companies—solving problems typically in the mechanical, electrical, optical domains. We provide multiphysics simulation solutions and optimization solutions and modeling capabilities, and that's a very promising area that's growing rapidly for us.

EDN: So when you say system-level, could you give an example of an application—large systems?

Rhines: Our biggest customers tend to be automotive and aerospace. We have a lot of usage there, but it goes down to medical equipment—even implantable medical equipment. We serve MEMS applications with electrical analysis and military applications that involve electromechanical systems and sometimes optical communications. So it is quite a diverse set of system companies in terms of size, but I think the focus for us started in military and aerospace and now has moved to medical instrumentation, but it requires domain expertise as well so we go one step at a time.

EDN: So it's not addressing low-cost consumer applications?

Rhines: Well, there are people who are use it for that. It's more a case of how much you want to invest in the modeling technology in order to get good, complete turnkey solutions as opposed to how much you're willing to build models as you go and develop the infrastructure as you move along. The places where they have really developed infrastructure to go with it tend to be the ones I mentioned—automotive, aerospace, medical.

EDN: The barrier for entry is fairly high?

Rhines: Well, modeling is always a barrier. The other barrier is simply user familiarity and bridging the gap between the domain expert and the design capability. Frequently you are crossing domains, and you are dealing with people who have expertise in different areas, and that's always a challenge—to get those people to work together to produce an optimized system. That's why system companies earn good margins—because the system means multiple technologies.

EDN: From a business perspective, as I walk around Semicon West people are almost euphoric—are you seeing that from an EDA perspective?

Rhines: The semiconductor industry, as you note, is red hot, and this has trickled back to the equipment manufacturers who, as you say, are euphoric because they are seeing their backlogs grow. And so what about EDA, why haven't you seen that grow as much? Well the first thing I would say is there are signs of growth. For example, EDAC  just released its first-quarter numbers [with revenue growing just less than 5% over Q1 2009]. It's not fantastic, but it's still growth. Typically EDA lags the semiconductor industry because in a recession the semiconductor companies typically cut back on everything except design, because they want to have product when the recession is over. And so their R&D as a percent of revenue becomes very high, and what they try to do coming out of recession is grow their revenue so their R&D will be back in line, and so they the ramp-up of spending in design at some period after the recovery starts. Typically it's a year to a year and a half, but it varies if you look though history. And so we are not really in that phase yet. Among the major EDA companies Mentor actually has been guiding to the highest growth rate, which is 7% plus, but on average the guidance is lower than that, and so that  suggests it could very well be a recovery just like the others, where you see strengthening as the semiconductor recovery continues.

EDN: Do you see share of market changing?

Rhines: Well, Mentor has been gaining a lot of market share. As you may have noted, Gary Smith EDA announced that Mentor has moved into the number two position, passing Cadence, and taking us up near the 25% market-share point. I believe Synopsys has also gained share, and I think the sum of the big three EDA companies as always has stayed constant—it's always about 75%.

EDN: Within Mentor, do you see a shift in revenues you get from semiconductor products vs. system-level products?

Rhines: I believe that first of all we see continued strengthening in system-level products, meaning system-design, analysis, embedded-software, thermal-analysis, and other system-level tools. And it will represent a growing share of our total revenue as we move out in time. When I look at the total markets, the embedded-software market, for example, is growing 15 to 20%—substantially faster than EDA, and as a result our embedded software business is growing faster than our traditional EDA business, and I expect at least over a multiyear average to see the systems business grow faster than the core EDA business.

EDN: In the design-for-test business, are there any issues there or gaps that need to be filled?

Rhines: That's an interesting area because design for test is one area of EDA that stayed strong and growing right through the recession. I think the thing that's been most exciting for us is the success of our LogicVision acquisition and the integration of scan-based test with built-in self test. The promise for the future is that we'll be able to take compressed test up to a factor of a 1000 or greater compression, compared to the date of introduction in 2001. With the capability to integrate built-in self test with compressed scan, I see a very fruitful roadmap ahead for growth of products and for continuing help to our customers in keeping their test costs at manageable levels while increasing their quality and their ability to quickly analyze and correct problems in their designs.

EDN: And will the 3-D chips with through-silicon vias require new DFT strategies?

Rhines: It will have to be supported with tools that address it, so there are will be large growth in known-good-die testing. In fact the tester people I talked to today said that's already happening. You are already seeing die testing preliminary to the die stacking process, and that's generating revenue for tester companies. The tests involve test programs, test vectors, test analysis—and that's all very good for the electronic design-automation industry, and particularly Mentor because we have such a very large share of the design-for-test EDA market today.