A new calculation for designing multilayer planar spiral inductors
A new, simple, and accurate expression lets you calculate the coupling factor between multilayer PCB inductors.
Jonsenser Zhao, Pulse -- EDN, July 29, 2010
| View as PDF |
Planar spiral inductors are less expensive than either chip or coil inductors for PCB (printed-circuit-board)-based designs. Accuracy in designing a spiral inductor is important because it is difficult to modify the inductor once you have built it on the PCB. Some formulas are available for calculating the spiral inductor for RF-IC applications with inductance of less than 100 nH on a single-layer design. For the application of HPNA (Home Phoneline Networking Alliance) or RF-telecom designs, which need inductances of more than 10 μH, no published paper or report accurately calculates spiral inductors with a large value in multiple layers.
Three options exist for designing large
planar spiral inductors on a PCB: Increase
the number of turns; increase the
inner diameter, DIN; or add layers and
increase the coupling between multilayers.
The first two options occupy more
area on the PCB, so the third option is
the best way to accommodate a large inductor
when there is limited PCB area.
Multilayer planar spiral inductors offer
several advantages over other inductors.
They have stable inductance, for example,
and, if the PCB has a fixed layout,
their inductance tolerance is less than
2%. Further, spiral inductors cost less than chip inductors and
require a less complex manufacturing process, making them
easier to manufacture with low yield loss.The traditional formula for calculating inductor size is accurate
for single-layer planar spiral inductors, but it does not
calculate the inductance for planar spiral inductors built on
multilayers and connected with via holes (Figure 1).
You can calculate a single-layer inductor’s value using Equation 1:
where N is the number of turns; μ0 is the vacuum permeability,
4π×10−7; ρ is the fill ratio, (DOUT−DIN)/(DOUT+DIN); DAVG
is the average diameter, (DIN+DOUT)/2; and C1
C2 are factors
depending on layout (Table 1). Figure 2 defines DIN (inner
diameter) and DOUT.
C2 are factors
depending on layout (Table 1). Figure 2 defines DIN (inner
diameter) and DOUT.
A multilayer inductor creates mutual inductance, however,
so 3-D-magnetic-simulation software cannot simulate
a multilayer inductor. Even if it could, the process would take
a long time, and the results would be inconsistent. Therefore,
you must use the following two equations for the coupling
value, KC, to obtain the total inductor value with a mutual inductance:
LTOTAL=L1+L2±2M,
and M=2×KC×
.You can obtain another simple and accurate expression for the inductance of a planar spiral by approximating the sides of the spirals using symmetrical current sheets of equivalent current densities (Reference 1). Although the accuracy of Equation 1 decreases as the ratio of space between traces to the trace width increases, it exhibits a maximum error of 8% for a space less than or equal to three times the width. Note that designers typically build practical integrated spiral inductors with space less than or equal to the width because smaller spacing improves the interwinding magnetic coupling and reduces the area the spiral consumes. In PCB design, this practice is not a concern because the intertrace spacing is normally less than the trace width.
Analysis of these equations and experimenting with large
inductors shows that Equation 1 is accurate, and the increasing
value of the inductor does not affect the accuracy of these
equations. The result shows an inductance close to the calculated
value, with the difference at high frequency due to
the actual distribution of parameters throughout the circuit
rather than the lumped-parameter analysis of the model (Figure 3). Thus, you can use Equation 1 to calculate a large,
single-layer inductor.
Calculations for a multilayer coupled planar spiral inductor are more complex than those for a single-layer spiral inductor. The coupling between the inductors on each layer is difficult to simulate because the coupling value depends on the number of turns of the inductor and the distance between the two layers. Experimenting over the range of inductor turns, N, with N equal to a 5- to 20-turns ratio, and the distance between the inductors on the two layers, X, with X equal to a 0.75- to 2-mm distance, yields Equation 2 to calculate the coupling factor:
where X is the distance in millimeters
between the inductors on the two
layers and N is the number of inductor turns that Figure 2
defines. The inductor turns of both layers must be the same
(Table 2).
With the coupling factor from Equation 2 and the single
planar-spiral-inductor calculation from Equation 1, you can
figure the total inductance of a two-layer inductor by using
the mutual-inductance formula (Reference 2).On a two-layer coupled inductor, you can calculate
the total inductance with the following layout information:
15.75 turns, 0.127-mm (5-mil) width and trace spacing, 1.0922-mm (43-mil) DIN, and 0.75-mm interlayer
distance. First, you must analyze the circular layout
to find DOUT and DAVG to obtain the single-layer inductance,
LS, and the coupling factor, KC: DOUT=DIN+2×
W+(W+S)×(2N−1)=8.9972; DAVG=(DIN+DOUT)/2=5.0927;
ρ=(DIN+DOUT)/(DOUT+DIN)=0.7855; LS=[(μN2DAVGC1)/2](ln(C2/ρ)+C3ρ+C4ρ2)]=10−6H=1 μH; KC=0.64. Per the mutual-inductance connection equations, the total inductance
is L1+L2+2×KC×==3.28 μH.
In a design with more than two layers, there are more coupling
factors between any two layers. You can use the same
method to obtain each coupling factor and then use the total
inductance per the mutual-inductance connection formulas.
You can also calculate a four-layer spiral inductor with
15.75 turns, a 5-mil-wide trace, a 5-mil trace spacing, and
a 43-mil circular inner diameter. Table 3 shows the stack
structure of the PCB. You must first calculate the single-layer
inductance, LS, which is 1 μH. It has six coupling factors:
KC12, KC13, KC14, KC23, KC24, and KC34. KC12=KC23=KC34=0.618,
KC13=KC24=0.459, and KC14=0.294. So the total inductance
is: L1+L2+L3+L4+(2×KC12+2×KC13+2×KC14+2×KC23+2×KC24+
2×KC34)×L1=10.132 μH. The four-layer inductor has a 10.1-
μH inductance.
=3.28 μH.In a design with more than two layers, there are more coupling
factors between any two layers. You can use the same
method to obtain each coupling factor and then use the total
inductance per the mutual-inductance connection formulas.
You can also calculate a four-layer spiral inductor with
15.75 turns, a 5-mil-wide trace, a 5-mil trace spacing, and
a 43-mil circular inner diameter. Table 3 shows the stack
structure of the PCB. You must first calculate the single-layer
inductance, LS, which is 1 μH. It has six coupling factors:
KC12, KC13, KC14, KC23, KC24, and KC34. KC12=KC23=KC34=0.618,
KC13=KC24=0.459, and KC14=0.294. So the total inductance
is: L1+L2+L3+L4+(2×KC12+2×KC13+2×KC14+2×KC23+2×KC24+
2×KC34)×L1=10.132 μH. The four-layer inductor has a 10.1-
μH inductance.Several samples with different sizes and structures verify
the new calculation and measure and compare samples. To
perform the verification, you must first increase the size of
the single-layer planar inductor and then increase the number
of turns from four or five to 15. You must also increase the
track width from 4 to 200 microns and increase DIN from 100
to 2400 microns. The inductance calculated using Equation
1 is 1.1 μH. Figure 4 shows the measured inductor frequency response, which is close to the theoretical calculation to a
frequency as high as 100 MHz. The Q value and self-resonant
frequency in figures 4 and 5 are better than that of the
same-value chip inductor. Normally, the chip inductor’s Q
value is only 15 to 20.
To verify the coupling factor, you build two equally sized,
1.1-μH planar spiral inductors on a two-layer PCB substrate
with a thickness of 0.8 mm. The calculated inductor value using
Equation 2 is 3.8 μH. Figures 6 and 7 show the frequency
response. The two-layer planar spiral inductor’s Q and self-resonant
frequency are better than that of a chip inductor with
the same value.
Figure 8 shows a fifth-order lowpass filter with two-layer
coupled planar spiral inductors using the new calculation for
the design of this filter. The performance of the filter matches
the simulation result and works for HPNA and other telecommunication
applications (Figure 9). The simplicity and
robustness of these calculations simplify circuit design and
optimization applications, which you can incorporate into
the computer-circuit model for spiral inductors.
| Acknowledgment |
| The author would like to thank Homer Feng, KB Ong, Paul Doyle, Andrew Zhang, and Bino Zhu for their valuable input and technical support during this project. |
|
References |
|
Author's Biography
Jonsenser Zhao is a senior design engineer at the
network division of Pulse’s Chinese development
center, where he is responsible for transformer, filter,
and splitter design. Zhao has a bachelor’s degree
in electronics from the Air Force Missile College
(Shaanxi, China). His interests include developing
designs for telecommunications applications.Talkback
-
I checked the four layer inductor design using my good old reference book J. Hak: Eisenlose Drosselspulen, Leipzig, K.F. Koechler Verlag 1938, 316 pages. (Reprint J.W. Edwards, Ann Arbor, Michigan 1944) and, using curves on page 256, ended up with about 10.7 uH using 16 turns per layer. The Hak's approach does not need any coupling factors, just the dimensions and the number of turns, but naturally does not lend itself for computer calculations because of the graph used.
Jouko Niiranen - 2010-2-8 05:32:57 PDT -
Thak you for your great effort; I find planar inductors very useful, but up until now I've been restricted to single layer designs.
Jon Fuge - 2010-30-7 03:57:45 PDT
