Measuring wideband-amplifier settling time
A novel circuit lets you measure output settling to 0.1% in 2 nsec.
Jim Williams, Linear Technology -- EDN, August 12, 2010
At A Glance
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You use wideband amplifiers in instrumentation, waveform-synthesis, data-acquisition, and feedback-control systems. To ensure a robust design for these systems, you must verify precision operation at high speeds. This requirement presents a difficult measurement challenge. Wideband operational amplifiers feature dc precision of 0.2-mV offset voltage with gain-bandwidth products of 400 MHz and slew rates of 2500V/μsec (Reference 1). IC designers face a trade-off between fast slew rates and short ring times. Fast-slewing amplifiers generally have extended ring times. This combination complicates your amplifier choice and the frequency compensation you use (see sidebar “Practical considerations for amplifier compensation”). Additionally, the architecture of very fast amplifiers usually dictates trade-offs, which degrade dc-error terms.
Settling time defined
It is relatively easy for you to verify amplifier dc specifications. Literature defines the measurement techniques you use. You need to use more sophisticated approaches to produce reliable ac specifications. Measuring anything at any speed requires care. Dynamic measurements are particularly challenging, and amplifier settling time is difficult to determine (references 2 through 7). Settling time is the elapsed time from an input application until the output arrives at and remains within a specified error band around the final value. Amplifier manufacturers usually specify it over a full-scale transition.
Settling time has three distinct components
(Figure 1). The delay time is
small and almost entirely due to the
amplifier’s propagation delay. No output
movement occurs during this interval. During slew time, the amplifier
moves at its highest speed toward the
final value. Ring time defines the region
during which the amplifier recovers
from slewing and ceases movement
within some defined error band. Measuring
settling times of nanoseconds requires
a careful approach and experimental
technique.
The traditional way for measuring
settling time is with a circuit that uses
the false-sum-node technique (Figure 2). The resistors and amplifier form a
bridge network. The amplifier output
steps to the input voltage when you
drive the input, assuming that the circuit
is using ideal resistors. During the
slew period, the diodes bound the settle
node, limiting the voltage excursion.
When settling occurs, the oscilloscope’s
probe voltage should be 0V. The
resistor divider’s attenuation causes the
probe’s output to be one-half of the settled
voltage.
In theory, this circuit should allow you to observe fast settling to small amplitudes. In practice, you cannot rely on it to produce useful measurements. The circuit has several flaws, including a requirement for the input pulse to have a flat top within the required measurement limits. Typically, you are interested in settling of less than 5 mV for a 5V step. No general-purpose pulse generator holds the output amplitude and noise within these limits. You cannot distinguish between generator-caused aberrations and amplifier-related ones.
The oscilloscope connection also presents problems. As probe capacitance rises, the ac loading of the resistor junction influences the observed settling waveforms. The excessive input capacitance of 1× probes makes them unsuitable for this measurement. A 10× probe’s attenuation sacrifices oscilloscope gain, yet its 10-pF input capacitance still introduces a significant lag at nanosecond speeds. If you use an active 1×, 1-pF FET (field-effect-transistor) probe, it largely alleviates this problem, but a more serious issue remains.
You use clamp diodes at the settle node to reduce the voltage swing during amplifier slewing. This approach is intended to prevent the circuit from overdriving the oscilloscope input. Unfortunately, the 400-mV drop across the Schottky diodes means that the oscilloscope will undergo an unacceptable overload (Reference 8). Oscilloscopes’ overdrive-recovery characteristics vary widely among models and brands, and manufacturers typically do not specify it. At 0.1% resolution, the oscilloscope typically undergoes a 10-times overdrive at 10 mV/division, making the desired 2.5-mV baseline unattainable.
With this arrangement, the measurement becomes hopeless at nanosecond speeds.
Thus, your measuring wideband amplifier settling time requires an oscilloscope that is somehow immune to overdrive as well as a flat-top pulse generator. The only oscilloscope technology that offers inherent overdrive immunity is the classic analog sampling oscilloscope. Do not confuse these scopes with modern digital sampling oscilloscopes that have overdrive restrictions (Reference 8). Several documents explain the operation of classic sampling oscilloscopes (references 9 through 13). Although you can buy these instruments used, their manufacturers no longer make them. You can, however, construct a circuit that borrows the overload advantages of classic analog-sampling-oscilloscope technology. You can also endow the circuit with features for measuring nanosecond settling times.
You can avoid the flat-top-pulse-generator requirement by switching current rather than voltage. It is easier to gate a quickly settling current into the amplifier’s summing node than to control a voltage. This approach eases the input pulse generator’s job, although it still must have a rise time of approximately 1 nsec to avoid measurement errors.
Practical measurement
A circuit that can measure wideband-amplifier
settling time shares attributes with the classic method, although some
new features appear (Figure 3). The oscilloscope
connects to the settle point
by a switch. You determine the switch’s
state by triggering a delaying pulse generator
from the input pulse. You arrange
the delayed pulse generator’s timing so
that the switch does not close until settling
is nearly complete. In this way,
you sample the incoming waveform in
both time and amplitude. No off-screen
activity occurs on the oscilloscope;
hence, you never subject the oscilloscope
to overdrive.
You control the switch at the amplifier’s summing junction with the input pulse. This switch gates current to the amplifier through a voltage-driven resistor. This approach eliminates the requirement for a flat-top pulse generator, although the switch must be fast and devoid of drive artifacts.
For more detail, you split the delayed
pulse generator into a delay block and a
pulse generator, which you can vary independently
(Figure 4). The input step
to the oscilloscope runs through a section
that compensates for the propagation
delay of the settling time’s measurement
path. Similarly, another delay
compensates the sample gate’s pulse-generator
propagation delay. This delay
causes a phase-advanced version of
the pulse that triggers the amplifier under
test to drive the sample gate’s pulse
generator. This approach improves
minimum measurable settling time by
making irrelevant the sample gate’s
pulse-generator propagation delay.
The most striking new aspects of Figure 4’s circuit are the diode bridge
switch and the multiplier IC. The diode
bridge’s balance combines with
matched, low-capacitance Schottky diodes
and high-speed drive to yield clean
switching. The bridge quickly switches current into the amplifier’s summing
point, with settling time within 1 nsec.
The diode clamp to ground prevents
excessive bridge-drive swings and ensures
that nonideal input-pulse characteristics
are nearly irrelevant.
The sample-gate multiplier IC has stringent requirements. It must faithfully pass wideband-signal-path information without introducing alien components, particularly those deriving from the switch-command channel that provides the sample-gate pulse. Conventional choices for the sample-gate switch would include FETs or a sampling diode bridge. But FETs’ parasitic gate-to-channel capacitances would result in large gate-drive-originated feedthrough into the signal path. For almost all FETs, this feedthrough is many times larger than the signal you are observing and would induce oscilloscope overload and obviate the switch’s purpose. The diode bridge is better; its small parasitic capacitances tend to cancel, and its symmetrical, differential structure results in low feedthrough. Practically, however, the bridge requires dc and ac trims and complex drive and support circuitry (references 3, 4, 7, and 14).
To avoid these problems, the sample-gate multiplier IC functions as a wideband high-resolution switch with low feedthrough. The great advantage of this approach is that you can maintain the switch-control channel inband. You hold the transition rate within the multiplier IC’s 250-MHz bandpass. The multiplier’s wide bandwidth means that you always control the switch command’s transition. There are no out-of-band responses, greatly reducing feedthrough and parasitic artifacts.
Settling-time circuitry
You let the input pulse switch the input
bridge through a delay network of
inverters, A, and a driver stage comprising
similar inverters, C (Figure 5).
The delay compensates the sample-gate
pulse generator’s delayed response. This
step ensures that the sample gate’s pulse
can occur immediately after the end of
the amplifier under test’s slew time. You
choose the delay range so that the sample-gate pulse can occur before the amplifier
slews. This capability is unused
in normal operation, although it guarantees
that you will always be able to capture the settling interval.
The C inverters form a noninverting driver stage you use to switch the diode bridge. You adjust various trims to optimize the driver output pulse shape (see sidebar “Settling-time circuit-trimming procedures”). This approach provides a clean, fast impulse to the diode bridge. This high-fidelity pulse is devoid of undamped components. It prevents radiation and disruptive ground currents from degrading the measurement noise floor. The driver also activates the B inverters, which supply a time-corrected input step to the oscilloscope.
The driver’s output pulse transitions through the 1N5712 diode clamp’s forward-voltage potential in less than 1 nsec. This transition causes an essentially instantaneous switching of the diode bridge. The cleanly settling current into the amplifier under test’s summing point causes a proportionate amplifier output movement. You set up a negative bias current at the amplifier’s summing point with a 1-kΩ resistor pulled to −5V. That current combines with the input current step to produce a −2.5 to +2.5V amplifier output transition. You feed this amplifier’s output to a voltage divider biased to 5V. You adjust the potentiometer to a nominal 500Ω so that when the amplifier under test transitions to −2.5V, the node clamped by the two Schottky diodes transitions to 0V. Buffer amplifier A1 unloads this clamped settle node and provides the settling-time signal to the AD835 multiplier IC.
The other signal path to the multiplier IC uses a 20-kΩ potentiometer to set a delay time of the input pulse. This potentiometer feeds three comparators, and you use a 2-kΩ potentiometer to set the delayed pulse width. This step sets the sample gate’s on-time. The Q1 stage forms the sample gate’s pulse into a clean, fast rise time. This technique furnishes pure, calibrated-amplitude, on/off switching instructions to the sample gate’s multiplier IC. Appropriate setting of the sample gate’s pulse delay means that the oscilloscope will not see any input until settling is nearly complete, eliminating oscilloscope overdrive. You adjust the sample window’s pulse width so that you can observe all the remaining settling activity. In this way, the oscilloscope’s output is reliable, and you can take meaningful data.
Performance results
The circuit performs admirably (Figure
6). Trace A is the time-corrected
input pulse, Trace B is the amplifier’s
output, Trace C is the sample gate’s
pulse, and Trace D is the settling-time
output. When you interpret the waveform
placement, note that Trace B appears
time-skewed relative to time-corrected
Trace A. This skew accounts for
Trace B’s false movement before Trace A’s ascent. When the sample gate’s pulse
goes high, the sample gate switches
cleanly. You can easily observe the last
20 mV of the amplifier’s slewing. You
can also see the entire ring time and the
amplifier settling nicely to a final value.When the sample gate’s pulse goes low, the sample gate switches off with only 2 mV of feedthrough. No off-screen activity occurs at any time, and you never subject the oscilloscope to overdrive.
You can adjust the vertical and horizontal scales of the oscilloscope to make the settling details more visible (Figure 7). You measure settling time from the onset of the time-corrected input pulse. Additionally, you calibrate the settling signal’s amplitude with respect to the amplifier, not the settle node. This approach eliminates ambiguity due to the settle node’s resistor ratio. Trace A is the time-corrected input pulse, and Trace B is the settling output. You can easily observe the last 50 mV of slew.
The amplifier settles within 5 mV, or
0.1%, in 9 nsec after you optimize the
amplifier under test’s feedback capacitor,
CF, (see sidebar “Practical considerations
for amplifier compensation”).It is good practice to adjust the sampling
window backward to the last 50 mV or so of amplifier slewing. This
step allows you to observe the onset
of ring time without encountering oscilloscope
overdrive. The sampling-based
approach provides this capability,
and it is a powerful measurement
tool. Slower amplifiers may require extended
delay, sampling-window times,
or both. You can use larger capacitor
values in the delayed pulse-generator
timing networks to meet these
requirements.
Verifying results
The sampling-based settling-time circuit appears to be a useful measurement approach. A good way to ensure confidence is to make the same measurement with an alternative method and see whether results agree.
Classic sampling oscilloscopes are
inherently immune to overdrive (Reference
8). You can use this feature
and attempt a settling-time measurement
directly at the clamped settle
node (Figure 8). The circuit heavily
overdrives a Tektronix type 661 with
4S1 vertical and 5T3 timing plug-ins,
but the instrument is ostensibly immune
to the insult (Figure 9). Trace A
is the time-corrected input pulse, and Trace B is the settle signal. Despite a
brutal overdrive, the oscilloscope responds
cleanly, giving a plausible settle
signal.
The two measurement methods do show nearly identical settling times and highly similar settling-waveform signatures. This agreement provides a high degree of credibility to the measured results. The noise floor and the signal feedthrough impose the 2-mV amplitude-resolution limit. The time resolution’s limit is about 2-nsec to 5-mV settling.
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Practical considerations for amplifier compensation
There are a number of practical considerations when you compensate the amplifier to get the fastest settling time (see Figure 1 in the main text). Once you choose an amplifier, the only settling variable you can change is the ring time by changing the amplifier’s compensation network. Because slew time is usually the dominant lag, it is tempting to select the fastest-slewing amplifier available. Unfortunately, fast-slewing amplifiers usually have extended ring times, which negate their speed advantage. If you damp out the ringing with large compensation capacitors, it results in protracted settling times.
The key to good settling times is to choose an amplifier with the right balance of slew rate and recovery characteristics and then properly compensate it. This is harder than it sounds because you can’t predict amplifier settling time or extrapolate it from any combination of data-sheet specifications. You must measure settling time in the intended configuration.
A number of terms combine to
influence settling time. They include
amplifier slew rate and ac dynamics,
layout capacitance, source
resistance and capacitance, and
the compensation capacitor. These
terms interact in a complex manner,
making predictions hazardous. Spice
aficionados should take notice. If
you replace the parasitic components
with a purely resistive source,
you still can’t readily predict amplifier
settling time. The parasitic-impedance
terms make a difficult
problem messier.
The only way to deal with the parasitic terms is to adjust the feedback compensation capacitor, CF. When you properly adjust the value of CF, it rolls off the amplifier’s gain at the frequency that permits the best dynamic response. You achieve the best settling results when you select the capacitor to functionally compensate for all the terms (Figure A).
Trace A is the time-corrected input
pulse, and Trace B is the amplifier’s
settle signal. The amplifier comes
cleanly out of slew and settles to
5 mV in 9 nsec. The sample gate
opens just after the second vertical
division. The waveform signature is
tight and nearly critically damped.
When you use too large a feedback
capacitor the settling is smooth,
although overdamped (Figure B), giving
you a 13-nsec penalty that results
in a 22-nsec settling time. Eliminating
the feedback capacitor results in a
severely underdamped response with
resultant excessive ring-time excursions
(Figure C). Settling time goes
out to 33 nsec. Using a feedback
capacitor that is too small results in
an underdamped response requiring 27 nsec to settle (Figure D). Note
that figures B, C, and D require
you to reduce the vertical scale to
capture the nonoptimal responses.
When you trim the feedback capacitor for optimal response, the source, stray, amplifier, and compensation-capacitor tolerances are irrelevant. If you don’t use individual trimming, you must consider these tolerances to determine the feedback capacitor’s production value. Stray and source capacitance and output loading, as well as the feedback capacitor’s value, affect ring time. The relationship is nonlinear, although some guidelines are possible. The stray and source terms can vary by ±10%, and the feedback capacitor is typically a ±5% component. These figures assume a resistive source. If the source has substantial parasitic capacitance, such as a photodiode or a DAC, this number can easily reach ±50%. Additionally, amplifier slew rate has a significant tolerance, which the data sheet states. To obtain a production-feedback-capacitor value, you determine the optimum value by individual trimming with the production-board layout. Remember that board-layout parasitic capacitance counts too. Then, factor in the worst-case percentage values for stray- and source-impedance terms, slew rate, and feedback-capacitor tolerance. Add this information to the trimmed capacitors’ measured value to obtain the production value. This budgeting is perhaps unduly pessimistic. The errors should sum in an rms (root-mean-square) fashion, not a purely additive way.
There are a number of practical considerations when you compensate the amplifier to get the fastest settling time (see Figure 1 in the main text). Once you choose an amplifier, the only settling variable you can change is the ring time by changing the amplifier’s compensation network. Because slew time is usually the dominant lag, it is tempting to select the fastest-slewing amplifier available. Unfortunately, fast-slewing amplifiers usually have extended ring times, which negate their speed advantage. If you damp out the ringing with large compensation capacitors, it results in protracted settling times.
The key to good settling times is to choose an amplifier with the right balance of slew rate and recovery characteristics and then properly compensate it. This is harder than it sounds because you can’t predict amplifier settling time or extrapolate it from any combination of data-sheet specifications. You must measure settling time in the intended configuration.
A number of terms combine to
influence settling time. They include
amplifier slew rate and ac dynamics,
layout capacitance, source
resistance and capacitance, and
the compensation capacitor. These
terms interact in a complex manner,
making predictions hazardous. Spice
aficionados should take notice. If
you replace the parasitic components
with a purely resistive source,
you still can’t readily predict amplifier
settling time. The parasitic-impedance
terms make a difficult
problem messier.The only way to deal with the parasitic terms is to adjust the feedback compensation capacitor, CF. When you properly adjust the value of CF, it rolls off the amplifier’s gain at the frequency that permits the best dynamic response. You achieve the best settling results when you select the capacitor to functionally compensate for all the terms (Figure A).
Trace A is the time-corrected input
pulse, and Trace B is the amplifier’s
settle signal. The amplifier comes
cleanly out of slew and settles to
5 mV in 9 nsec. The sample gate
opens just after the second vertical
division. The waveform signature is
tight and nearly critically damped.
When you use too large a feedback
capacitor the settling is smooth,
although overdamped (Figure B), giving
you a 13-nsec penalty that results
in a 22-nsec settling time. Eliminating
the feedback capacitor results in a
severely underdamped response with
resultant excessive ring-time excursions
(Figure C). Settling time goes
out to 33 nsec. Using a feedback
capacitor that is too small results in
an underdamped response requiring 27 nsec to settle (Figure D). Note
that figures B, C, and D require
you to reduce the vertical scale to
capture the nonoptimal responses.When you trim the feedback capacitor for optimal response, the source, stray, amplifier, and compensation-capacitor tolerances are irrelevant. If you don’t use individual trimming, you must consider these tolerances to determine the feedback capacitor’s production value. Stray and source capacitance and output loading, as well as the feedback capacitor’s value, affect ring time. The relationship is nonlinear, although some guidelines are possible. The stray and source terms can vary by ±10%, and the feedback capacitor is typically a ±5% component. These figures assume a resistive source. If the source has substantial parasitic capacitance, such as a photodiode or a DAC, this number can easily reach ±50%. Additionally, amplifier slew rate has a significant tolerance, which the data sheet states. To obtain a production-feedback-capacitor value, you determine the optimum value by individual trimming with the production-board layout. Remember that board-layout parasitic capacitance counts too. Then, factor in the worst-case percentage values for stray- and source-impedance terms, slew rate, and feedback-capacitor tolerance. Add this information to the trimmed capacitors’ measured value to obtain the production value. This budgeting is perhaps unduly pessimistic. The errors should sum in an rms (root-mean-square) fashion, not a purely additive way.
Settling time circuit trimming procedures
You trim the settling time circuit to achieve its quoted performance. The trims fall into four loosely defined categories. These are current switch bridge drive pulse shaping, circuit delays, sample gate pulse purity, and sample gate feedthrough/dc adjustments. The trims require considerable care in instrumentation selection as well as thoughtful wideband probing and oscilloscope measurement technique (references a to e).
Bridge drive trims
You trim the current switch bridge drive first. First disconnect all 5 bridge drive related trims and apply a 5V, 1MHz, 10 to 15ns wide pulse at the circuit input. The paralleled “C” inverter output viewed at the 43V back termination’s undriven end should resemble Figure A1. Waveform edge times are fast but poorly controlled parasitic excursions risk corrupting the measurement noise floor and you must eliminate them. 
Reconnect all 5 trims and adjust them according to their titles (Figure A2). There is some interaction between the adjustments. Figure A2’s edge times are slightly slower than Figure A1’s, but still pass through the 1N5712 clamp level in less than 1ns.
Delay determination and compensation
The settling time circuit utilizes an adjustable delay network to correct the input pulse for delays in the signal-processing path. Typically, these delays introduce errors approaching 10ns, so you must provide an accurate correction. Setting the delay trim involves observing the network’s input-output delay and adjusting for the appropriate time interval. Determining the appropriate time interval is somewhat more complex.
In the circuit there are three delay measurements you are interested in. The current switch driver to amplifier-under-test negative input, the amplifier-under-test output to circuit output, and the sample gate multiplier delay. The delay from the current switch driver to the amplifier-under-test input measures 250ps (Figure A5). 
There is an 8.4ns delay from the amplifier-under-test output to circuit output (Figure A6). The sample gate multiplier delay is 2ns Figure A7.
These measurements indicate a current switch driver-to-circuit output delay of 8.65ns. You implement the correction by adjusting the 1kV trim in the “Signal Path Delay Compensation” network for that amount.
Similarly, when you use the sampling oscilloscope method, the relevant delays are from Figure A5 plus A6 minus Figure A7, for a total of 6.65ns. You adjust this into the signal path delay compensation network when you take the sampling oscilloscope-based measurement.
The “Sample Gate Pulse Generator Path Delay Compensation” trim is less critical. The sole requirement is that it overlap the sample gate pulse generator’s delay. Setting the 1kV potentiometer in the “A” inverter chain to 15ns satisfies these criteria. This completes the delay-related trims.
Sample gate pulse purity adjustment
You adjust the Q1 sample gate pulse edge-shaping stage for an optimized front corner, minimum rising edge time, pulse top smoothing and 1V amplitude with the indicated trims. You observe the adjustments at the sample gate multiplier IC’s “X” input (Figure A8). The pulse’s 2ns rise time promotes rapid sample gate acquisition but remains within the multipliers 250MHz bandwidth, assuring freedom from out-of-band parasitic responses. The clean, 1V amplitude pulse top provides a calibrated, consistent multiplier output devoid of aberrations which would masquerade as settling signal artifacts. The pulse fall time is irrelevant. It is not germane to the measure-ment and its clean falling transition assures controlled multiplier turn-off, precluding off-screen excursions.
Sample gate path optimization
The sample gate path adjustments are the final trims. First, put in 5V dc to the pulse generator input in order to lock the amplifier-under-test into its 22.5V output state. Adjust the “settle node zero” trim for zero volts within 1mV at A1’s output. Next, restore the pulsed circuit input, disconnect the settle node from A1 and ground A1’s input with a 750V resistor. The response is not ideal before trimming (Figure A9). Ideally, the circuit output (trace B) should be static during sample gate (trace A) switching. The photo reveals errors; correction requires trimming dc offset and dynamic feedthrough related residue. You eliminate the dc errors by adjusting the “X” and “Y” offset trims for a continuous trace B baseline regardless of trace A’s sample gate pulse state. Additionally, set the output offset adjustment for minimum multiplier baseline offset voltage. You set the sample gate gain to unity by shutting off the input pulse generator, applying 5V dc to C2’s “1” input and forcing 1.00V dc at the previously inserted 750V resistor. Under these conditions, you adjust “scale factor” for a 1.00V dc output. After completing this step, remove the dc bias voltages and the 750V resistor, reconnect the settle node, and restore the pulsed input.
You accomplish the feedthrough compensation with “time phase” and “amplitude” trims. These adjustments set timing and amplitude of the feedthrough correction applied at the multiplier IC’s “Z” input (Figure A10). This shows the dramatic effect of your dc and feedthrough trims on the pre-trim errors of Figure A9.
Measurement limits and uncertainties
The circuit’s post-trim response includes a flat baseline and greatly attenuated feedthrough. The measurement defines the circuit’s minimum amplitude resolution at 2mV. In another test, you disconnect A1’s input from the settle node and bias it at 20mV dc via a 750V resistor to simulate an infinitely fast settling amplifier (Figure A11). The circuit output (trace B) settles within 5mV in 2 nanoseconds, arriving inside the 2mV baseline noise limit in 3.6 nanoseconds. This data, taken with sample gate conduction beginning immediately after the time corrected input (trace A) rises, defines the circuit’s minimum time resolution limit. Uncertainties in the quoted time and amplitude resolution limits are primarily due to delay compensation limitations, noise and residual feedthrough. Considering likely delay and measurement errors, a time uncertainty of 6500 picoseconds and a 2mV resolution limit is realistic. Noise averaging would not improve the amplitude resolution limit because it is imposed by feedthrough residue, a coherent term.
You trim the settling time circuit to achieve its quoted performance. The trims fall into four loosely defined categories. These are current switch bridge drive pulse shaping, circuit delays, sample gate pulse purity, and sample gate feedthrough/dc adjustments. The trims require considerable care in instrumentation selection as well as thoughtful wideband probing and oscilloscope measurement technique (references a to e).
Bridge drive trims
You trim the current switch bridge drive first. First disconnect all 5 bridge drive related trims and apply a 5V, 1MHz, 10 to 15ns wide pulse at the circuit input. The paralleled “C” inverter output viewed at the 43V back termination’s undriven end should resemble Figure A1. Waveform edge times are fast but poorly controlled parasitic excursions risk corrupting the measurement noise floor and you must eliminate them. Reconnect all 5 trims and adjust them according to their titles (Figure A2). There is some interaction between the adjustments. Figure A2’s edge times are slightly slower than Figure A1’s, but still pass through the 1N5712 clamp level in less than 1ns.Delay determination and compensation
You next trim the circuit delays. Before making these measurements and adjustments, you must correct the probe/oscilloscope channel-to-channel time skew. Figure A3 shows 40ps time skew error with both channel probes connected to a 100ps risetime fast pulse source. There are several fast pulse sources that you can use (reference e). 
You correct the error by utilizing the oscilloscopes vertical amplifier variable-delay feature. In this case the oscilloscope amplifier is a Tektronix 7A29, option 04, installed in a Tektronix 7104 mainframe (Figure A4). This correction permits you to make high-accuracy delay measurements. You should also verify the oscilloscope time base for accuracy (reference e).
You correct the error by utilizing the oscilloscopes vertical amplifier variable-delay feature. In this case the oscilloscope amplifier is a Tektronix 7A29, option 04, installed in a Tektronix 7104 mainframe (Figure A4). This correction permits you to make high-accuracy delay measurements. You should also verify the oscilloscope time base for accuracy (reference e).The settling time circuit utilizes an adjustable delay network to correct the input pulse for delays in the signal-processing path. Typically, these delays introduce errors approaching 10ns, so you must provide an accurate correction. Setting the delay trim involves observing the network’s input-output delay and adjusting for the appropriate time interval. Determining the appropriate time interval is somewhat more complex.
In the circuit there are three delay measurements you are interested in. The current switch driver to amplifier-under-test negative input, the amplifier-under-test output to circuit output, and the sample gate multiplier delay. The delay from the current switch driver to the amplifier-under-test input measures 250ps (Figure A5). There is an 8.4ns delay from the amplifier-under-test output to circuit output (Figure A6). The sample gate multiplier delay is 2ns Figure A7.These measurements indicate a current switch driver-to-circuit output delay of 8.65ns. You implement the correction by adjusting the 1kV trim in the “Signal Path Delay Compensation” network for that amount.
Similarly, when you use the sampling oscilloscope method, the relevant delays are from Figure A5 plus A6 minus Figure A7, for a total of 6.65ns. You adjust this into the signal path delay compensation network when you take the sampling oscilloscope-based measurement.The “Sample Gate Pulse Generator Path Delay Compensation” trim is less critical. The sole requirement is that it overlap the sample gate pulse generator’s delay. Setting the 1kV potentiometer in the “A” inverter chain to 15ns satisfies these criteria. This completes the delay-related trims.
Sample gate pulse purity adjustment
You adjust the Q1 sample gate pulse edge-shaping stage for an optimized front corner, minimum rising edge time, pulse top smoothing and 1V amplitude with the indicated trims. You observe the adjustments at the sample gate multiplier IC’s “X” input (Figure A8). The pulse’s 2ns rise time promotes rapid sample gate acquisition but remains within the multipliers 250MHz bandwidth, assuring freedom from out-of-band parasitic responses. The clean, 1V amplitude pulse top provides a calibrated, consistent multiplier output devoid of aberrations which would masquerade as settling signal artifacts. The pulse fall time is irrelevant. It is not germane to the measure-ment and its clean falling transition assures controlled multiplier turn-off, precluding off-screen excursions.Sample gate path optimization
The sample gate path adjustments are the final trims. First, put in 5V dc to the pulse generator input in order to lock the amplifier-under-test into its 22.5V output state. Adjust the “settle node zero” trim for zero volts within 1mV at A1’s output. Next, restore the pulsed circuit input, disconnect the settle node from A1 and ground A1’s input with a 750V resistor. The response is not ideal before trimming (Figure A9). Ideally, the circuit output (trace B) should be static during sample gate (trace A) switching. The photo reveals errors; correction requires trimming dc offset and dynamic feedthrough related residue. You eliminate the dc errors by adjusting the “X” and “Y” offset trims for a continuous trace B baseline regardless of trace A’s sample gate pulse state. Additionally, set the output offset adjustment for minimum multiplier baseline offset voltage. You set the sample gate gain to unity by shutting off the input pulse generator, applying 5V dc to C2’s “1” input and forcing 1.00V dc at the previously inserted 750V resistor. Under these conditions, you adjust “scale factor” for a 1.00V dc output. After completing this step, remove the dc bias voltages and the 750V resistor, reconnect the settle node, and restore the pulsed input.You accomplish the feedthrough compensation with “time phase” and “amplitude” trims. These adjustments set timing and amplitude of the feedthrough correction applied at the multiplier IC’s “Z” input (Figure A10). This shows the dramatic effect of your dc and feedthrough trims on the pre-trim errors of Figure A9.Measurement limits and uncertainties
The circuit’s post-trim response includes a flat baseline and greatly attenuated feedthrough. The measurement defines the circuit’s minimum amplitude resolution at 2mV. In another test, you disconnect A1’s input from the settle node and bias it at 20mV dc via a 750V resistor to simulate an infinitely fast settling amplifier (Figure A11). The circuit output (trace B) settles within 5mV in 2 nanoseconds, arriving inside the 2mV baseline noise limit in 3.6 nanoseconds. This data, taken with sample gate conduction beginning immediately after the time corrected input (trace A) rises, defines the circuit’s minimum time resolution limit. Uncertainties in the quoted time and amplitude resolution limits are primarily due to delay compensation limitations, noise and residual feedthrough. Considering likely delay and measurement errors, a time uncertainty of 6500 picoseconds and a 2mV resolution limit is realistic. Noise averaging would not improve the amplitude resolution limit because it is imposed by feedthrough residue, a coherent term.| References |
a. Williams, Jim, APPENDIX E, “BREADBOARDING, LAYOUT AND CONNECTION TECHNIQUES.” “30 Nanosecond Settling Time Measurement for a Precision Wideband Amplifier,” Linear Technology Application note AN79, Sep 1999.b. Williams, Jim, sidebar “About low-impedance probes: when to roll your own and when to pay the money”, “Diode-turn-on-time-induced failures in switching regulators,” EDN, Jan 8, 2009. |
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