Designing for EOL with an ASIC

In industries where product life cycles last a decade or more, the challenges and costs associated with component obsolescence and EOL (end of life) are significant. Engineering teams can address these issues through careful planning and ASIC design.

Mike Walsh, On Semiconductor -- EDN, August 25, 2010

The obsolescence of older processes and larger geometries is largely forced by the consumer and communications industry’s insatiable need for smaller, higher-performance, more-efficient, and more-integrated devices. However, in many other markets—including the military, aerospace, automotive, and industrial sectors—the pace of change is not as rapid and there is, by necessity, much more emphasis on long-term product availability and support. The accessibility of such support, however, is dependent on a number of factors ranging from the willingness of the supplier to maintain investment in older technologies to the engineering team’s specific design and layout tools and methodologies. Furthermore, while the obsolescence of a “standard” component (such as a microcontroller) may cause challenges at some point in the future, the EOL of a complex ASIC, that has been developed at great cost for a specific application, can be expensive and difficult to overcome.

Because of this, engineers tasked with the development of ASICs and SOC (system-on-chip) devices for these slower-paced industry sectors need to carefully approach their design with more than just device functionality, specification, and performance in mind. They should also have a clear view of the likely longevity of the technology on which their design is based and how that longevity matches the lifetime goals for their particular product, as well as an understanding of the risks and costs that could ensue if an EOL condition were to arise. In particular, they should be looking to make design decisions with a view to how they can mitigate those risks and costs in the future.

The ASIC EOL gamble

EOL is a term often used to describe the end of the useful life of a component—when the device has been used for such a protracted period that it is no longer functioning as originally intended. However, in terms of ASICs, EOL relates to the situation where an ASIC supplier has made the decision to discontinue the semiconductor process on which that specific ASIC solution is based. In general, this leaves the OEM with two choices. The first is to obtain a large volume of the existing ASIC, in what is described as a “last-time buy,” and the second is to retarget the ASIC design to a new process node.

Last-time buys have their own problems: An OEM will often find it hard to know the exact volume of product that will be needed in the future, while the unanticipated purchase of a large number of components for future production, and the up-front expenditure that comes with it, is certain to have a very visible impact on the company’s short-term bottom line. Moreover, depending on the targeted application lifetime, the last-time-buy option may simply be putting off the inevitable migration to a new process.

Retargeting the design to a new process, however, leads to the potential of incurring significant NRE (nonrecurring engineering) costs connected with refabrication and, possibly, additional redesign to ensure compatibility with the new process geometry. This, in turn, demands significant design and engineering resources; project time for design, simulation, verification, fabrication, and testing; and the need to revive expertise and design knowledge for a legacy design where the original design team is unlikely to still be available. Further complications arise for devices that have received qualification to automotive, military, aerospace, and other key standards, as any replacement ASIC will have to be fully requalified—a process that can take many months to complete. As a result, it can be seen that the “total cost of ownership” of an ASIC for a long-term design does not simply come down to the NRE costs incurred at the beginning.

Of course it could be argued that these concerns aren’t true engineering issues, and it is certainly valid to say that they do not have an impact on immediate design requirements, such as performance, integration levels, board space, and power consumption. However, in today’s electronics industry the reality is that it is incumbent on engineering teams to deliver requisite functionality in all of these areas in the most cost-effective manner possible. This demands consideration of ways to keep long-term cost of ownership down, not simply to minimize the original NRE investment. Among the important factors influencing these lifetime costs are the choice of process geometry and the physical ASIC architecture itself.

Many of the design practices that most ASIC designers consider “good” actually lend themselves to facilitating the conversion process in the event of device migration due to process EOL. That said, there are many other specific issues that can help in migration that have less cost and a higher probability of success.

Core power-supply flexibility

Operating voltage is typically determined by whatever process technology is chosen for an ASIC. Independent core supply regulation breaks the dependency between operating voltage and process by separating chip source and core voltages. Not always an option due to cost, this feature often works well for situations where the ASIC environment will not support the core voltage of the migrated ASIC. With simple up-front consideration, a board can be designed to easily provide an independent supply for the ASIC core and then allow for easy changes to that voltage for future migration to a new technology if needed.

IP issues

The use of hard IP can severely limit the effectiveness of ASIC-migration choices in the future. Utilizing soft IP that can be retargeted to a different process technology allows easier ASIC migration later on. The same premise holds true for proprietary IP. Using IP specific to an ASIC vendor or process technology can irrevocably lock that design to that vendor (and often that technology node), making redesign necessary to accommodate ASIC-migration choices, and incurring time and cost penalties as a result. To avoid this situation, use standard-based hard IP wherever possible, as it increases the chances that newer technologies will have support for the standards being used. In many cases, even if the standard has moved to a new revision in the newer technology (from PCI to PCIX, for example), the new versions remain backward compatible to the older versions. If possible, full custom hard IP, unlikely to be available off the shelf in a new technology, should be avoided.

Concerning documentation

Adequate documentation can often be the key to a successful design migration, whether measured by schedule, cost, or number of turns to produce correct functionality. Documentation allows the ASIC-migration team to understand the design particulars without having to learn them. Thus, the expense, the time period needed, the cost, and the number of tape-outs can often be cut down just by keeping detailed information ready for an eventual EOL migration. An ASIC house experienced in migration procedures can provide an exhaustive list of desirable documentation, such as design specifications (including all operating conditions), RTL or Verilog netlists, power requirements, and STA (static-timing-analysis) scripts (including noise and signal sensitivity information).

Synchronous design techniques

Synchronous design techniques allow an ASIC house engaged in a migration project to readily employ STA to verify timing without dealing with inter-clock domain relationships. Using a single external clock, with synchronous inputs and a single external set/reset, helps STA be effective and comprehensive. The employment of synchronous RAMs allows STA to effectively check timing through these blocks, as well.

Managing multiple clock domains

In the event that synchronous design techniques are not practical, there are measures that can be taken to help limit the exposure that asynchronous design situations pose to ASIC migration. If multiple clock domains exist, attempts should be made to ensure that each domain is fully synchronous. It is important that a reset strategy is decided for all domains—either by using a synchronous reset for all domains or by allowing all domains to come out of reset before functionality is relied upon.

Managing the derived skew from clock dividers or combinational clock sources can be carried out by fully specifying and documenting these situations in STA. Pictures can be worth a thousand words when it comes to understanding clock relationships; simple schematics or other forms of graphical representation of clock networks can save time and effort when these networks need to be resynthesized and verified in a migrated ASIC.

Data transfer across clock domains


Latches and combinational feedback loops

Latches pose an issue for STA and add to DFT (design-for-testability) overhead. These elements are replaceable by flops and should be avoided as much as possible. Combinational feedback loops also pose STA problems, can cause metastability issues in a circuit, and are replaceable by a flop. These situations often have to be found and inoculated when migrating an ASIC, so removing them in the first place often saves this step.

Build in margin

Sometimes including a build-in margin is easier said than done. However, adequate timing margin allows for easier ASIC migration with less redesign. While resynthesis can often bridge this gap effectively through re-architecture and restructuring, creating a system-timing budget that includes a potential EOL migration some time down the road can keep migration options open. Done effectively, a system-timing budget that includes adequate margin can allow for ASIC migration into a larger geometry.

RTL-coding guidelines

Whether handing off RTL to retarget to a different technology or handing off a netlist because the RTL is not available, good coding techniques used in the source code can help make the design and verification of the migrating ASIC less costly. There are some simple guidelines to follow: Put I/O in the top-level ring; register all module outputs, single clock, and reset per module; contain each speed-critical path in a single module; and isolate memories in hierarchical modules.

Build predictable pulse generators


When a migration needs to happen

When the unavoidable migration needs to occur as a result of an EOL, techniques for handling these situations are worth discussing.

Design a drop-in replacement to the existing design and minimize the effort to replace the EOL device. Scope out the new design to include only a direct match of the previous design. This would include functional matching, signal-integrity matching, software matching, and footprint matching.

One might consider re-spinning of the board versus trying to design a drop-in replacement to the existing design. The overall time, effort, and cost required to do this may be lower in certain cases. The scope of re-spinning the board could also be expanded to include cost-reduction efforts, performance and feature enhancements, and bug fixes. Each of these efforts certainly needs to be evaluated on a case-by-case basis, and the trade-offs would need to be balanced with time, cost, and risk. Regardless of the migration path that is chosen, it is critical to choose a vendor that has migration experience with a proven design track record.

Supplier considerations

Engineers planning their ASIC EOL strategy will also need to perform due diligence on the chosen ASIC vendor beyond simple availability of process and IP. Put quite simply, experience counts. ASIC companies exist that boast great track records and have built up years of valuable expertise in migrating IP, blocks, and functionality, with proven flows and methodologies. This knowledge can be crucial when faced with an EOL situation where migrating an ASIC is necessary. ASIC houses with seasoned and experienced engineering staffs can significantly reduce the amount of customer engineering effort that needs to be spent migrating an ASIC, mitigate risks to first-time-right silicon, and minimize schedule/costs. One factor that an engineering team must consider when it comes to developing an ASIC for applications with longer lives is whether to choose a fabless supplier or work with a supplier whose ASIC business is based on an IDM (integrated-device-manufacturer) model. For quite a while, it has been true that a growing number of semiconductor developments have come from fabless companies, but the fact is that they cannot have the share of mind with a foundry as a company that has its own fabrication facilities will possess. This situation has a number of implications. First, they have no control over the longevity of the process on which they base their designs. Second, there is no guarantee that the IP offered by a fabless company is compatible across multiple geometries, causing scaling issues. Using a fabless company for longer-lasting ASIC designs, therefore, can build in additional EOL risk.

Even when choosing the IDM route, there are still significant factors to consider. Does, for instance, the chosen vendor have a proven track record in markets that require longevity? A vendor that supports markets such as military, aerospace, and automotive will typically be better equipped to design and support ASIC projects that require long-term availability. Then, should an EOL situation occur, does that supplier have the experience to migrate the design from one technology to another? Some companies, for example, offer services that can migrate IP blocks and functionality using proven techniques. Such techniques, combined with the good design practices described above, can significantly minimize the engineering effort needed to migrate a legacy design to a new technology.

Finally, it is also worth looking at the balance of analog versus digital integration available from the vendor. Complex analog blocks typically require much higher levels of investment in the underlying process technology than their digital counterparts, and 180 nm remains at the leading edge for analog implementations. Companies focusing on analog processing and IP will, therefore, be looking to recoup investment by keeping 180 nm and other major technology nodes as long as possible.

Conclusion

While it is commonly reported that ASIC-design starts are down, it is clear that many of the projects that do begin are significant in size (representing huge numbers of units) and are expected to deliver long-life operation. The dangers that are associated with EOL are therefore high, and it is thus vital for design engineers to consider EOL as an important part of their ASIC-design process.

Choice of common technology nodes with a view to long-term availability and support should be one of the first considerations. Whether to use a fabless supplier or a vertically integrated vendor with its own fabrication facilities will also be important, as will the company’s experience with markets that require long-term support. Once the technology node and supplier are chosen, the engineering team must then design the ASIC using techniques such as partitioning or synthesizable IP blocks in such a way that the potential risks associated with EOL conditions can be alleviated wherever possible. This approach, combined with ensuring that a supplier has the necessary experience in migrating designs from one technology to another, will help engineers overcome the challenges of ASIC EOL.

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