Satisfying teenagers while making money in an era of ‘smart everything'

CEOs discussing collaboration during a panel at GlobalFoundries' Global Technology Conference agreed that teenagers are the drivers behind much of the collaboration work that is done in the semiconductor ecosystem of today.

By Ann Steffora Mutschler, Contributing editor -- EDN, September 2, 2010

SANTA CLARA, CA - In a lighthearted moment of clarity, CEOs discussing collaboration during a panel at GlobalFoundries' Global Technology Conference Wednesday agreed that teenagers are the drivers behind much of the collaboration work that is done in the semiconductor ecosystem of today.

In all seriousness, of course, it is not only teenagers demanding multimedia applications, but they do join systems houses and other end users in pushing IP and EDA companies along with foundries to continue innovating to allow the applications of tomorrow. On the road to high-volume 28-nm manufacturing for next-generation products ranging from smart mobile devices to high-performance wired applications, the need for close collaboration continues to grow between design and manufacturing.

In this vein, Cadence Design Systems' CEO Lip-Bu Tan has observed his sons multitasking on their electronic devices and realized it is exactly these activities that drive the industry to create hardware/software design platforms, virtualization of that along with parallel development - all of which are extremely challenging and will require collaboration to get the job done.

Another example of what users want today is what Dr Aart de Geus, chairman and CEO of Synopsys Inc, calls the era of "smart everything." His example is one in which you are driving in San Francisco, looking for a vegetarian restaurant, need to find parking, and then pay for that parking in a secure way. The ability to do this on one single device calls into play many layers of software to perform database searches, GPS, financial, and other functions.

De Geus pointed out that this plays neatly into the theme of collaboration for technology and economics, which he has termed "techonomics."

"It's a great collaboration because we are in the midst of what I believe is a fabulous new wave of electronics going forward, but it has left me wondering what the fundamental principles in this equation is that governs how we should be managing things."

On the economic side, de Geus pointed out that we are entering this smart everything era, in which everything is smart, connected, and truly requires the collaboration of every technology ever invented.

"What drives this is, if you look at successful products, it's always the same algorithm which is that you have to have a better mousetrap, or if not better, at least have it sooner than the other guy; if not sooner, make it cheaper than the other guy," he continued.

"Looking at the massive downturn we just went through, we immediately saw the market go to cheaper, then to better, and I would argue we are on the sooner part," de Geus offered.

Then, on the technology side, he explained, "the one principle that has driven productivity for the last 35 years is smart abstractions. You've seen the abstractions being enabled fundamentally by key technology breakthroughs that have moved us from transistors to gates to RTL to SOC and now to entire hardware/software systems.

"If there is one principle underneath this that applies every time is that you can not move to the next level unless you can model what's underneath," de Geus continued. "If you can model, maybe you can verify. And if you can verify, maybe you can improve. This is such a fundamental algorithm that I can look back and see it applies to everything we have ever done in our shop."

Even so, he reminded, collaboration is multidimensional. "If you look at the world from system all the way down to silicon, we find many partners. ... They have many interactions and the amount and the sophistication of the data [if you work your way up from silicon] is quite substantial. It has a center of gravity, though, it's an increasing integrated optimized design flow and I think we're doing quite well. Chips are coming out and we are in the steady improvement phase of smaller, faster, lower power, more manufacturable, etc."

The big change in the last few years, de Geus asserted, is the massive amount of software around these multicore products. There, the big key is whether it will be possible to model upward, so these people can start doing their work before the chips are done, before the rest of the design is done.

Embrace collaboration as early as possible

Collaboration became part of ARM's DNA early on, when the company was still working in a converted barn in an obscure village in Cambridge, England, explained panelist Simon Segars, executive VP and GM of ARM's physical IP division. "The CEO at the time drilled into us that there was no way on earth that we were going to be able to do everything ourselves so we really had to work on partnerships and build a strong ecosystem." Now, ARM's ecosystem has approximately 750 member companies all working toward the goal of making it as easy as possible to build an ARM-based SOC, he said.

Along these lines, Segars said ARM's work with GlobalFoundries over the past few years has been to enable implementation of very high performance ARM-based SOCs. The companies work together to specify and develop physical IP libraries of standard cells, memories, and I/Os, then work together to silicon-prove them and then make them available to end users through ARM's Web portal.

Further, ARM and GlobalFoundries announced during the conference that following two and a half years of joint work, the foundry has taped-out a qualification vehicle based on the ARM Cortex-A9 dual processor. The companies claimed this as an industry first on 28-nm High-K Metal Gate (HKMG) technology. The foundry said this Technology Qualification Vehicle (TQV) will allow it to optimize its 28-nm HKMG process for customer designs based on the dual-core ARM processor, meant to provide a faster path to market.

The jointly developed TQV reached tapeout last month at GlobalFoundries' Fab 1 in Dresden, Germany, with silicon results expected back from the fab late this year.

The TQV is designed to emulate a product-like SOC in every way, allowing for maximum frequency analysis and short turnaround time between design cycles with DFT features allowing Silicon-Spice correlation of Cortex-A9 critical paths and bit-mapping of cache memories at gigahertz speed, according to the companies.

Collaborative R&D allows companies to leverage joint work for competitive advantage

Giving an interesting insight into one of the world's largest semiconductor companies, earlier in the day Jean-Marc Chery, executive VP and CEO of STMicroelectronics, offered insights into the company's collaborative R&D approach.

"There is a very obvious reason that we are here today as ST. It is because ST is convinced that technology R&D and manufacturing brings us competitive advantage in the field of multimedia convergence in all applications where we want to be an industry leader. This drives our determination and motivation in this domain."

Consistent with ST's asset-light strategy and economical model, Chery noted that ST does use straight foundry services or IP provider services with its internal R&D or manufacturing for certain applications because it offers faster time-to-market or better innovation.

ST invests operating effort in technology R&D because it brings competitive innovation, which means fast time-to-market along with innovation. As well, it allows ST a competitive supply chain including multi-synchronized fabs.

ST controls its R&D process so the full R&D value chain of the R&D process acts differently across the process flow, Chery explained. This is broken into four steps: fundamental research, advanced semiconductor R&D, technology development, and manufacturing. This is further segmented into technology innovation (fundamental research and advanced semiconductor R&D) and technology operations (technology development and manufacturing).

He explained that ST's approach in technology innovation accelerates innovation by leverages third parties including foundations and advanced R&D through joint research with academia and research institutes such as CEA LETI and IMEC. Advanced CMOS R&D for both low power and general purpose is done through the International Semiconductor Development Alliance (ISDA).

In terms of its technology operations, ST balances its internal operations with third parties including ISDA for advanced CMOS, Agrate, and Crolles for analog and derivatives, and Agrate/Crolles/Greater Noida for distributed design enablement.

"We consider this model of collaborative R&D across the value chain of R&D. First on advanced and fundamental research ST is able through this cooperation to leverage the best innovation because this is our choice of materials, device integration, process steps which will create the ideal balance in terms of key performance indexes," he noted.

"The advantage we enable from this collaborative R&D is to mitigate risk because definitively when you have positive confrontation between partners, which happens from time to time, on the other side you mitigate risk because it is when you have a very positive and open confrontation of technical assessment, advice and so forth at the end you will know it's the right decision," Chery concluded.