A primer for successful integration of complex hard IP in physical design

The designer must address several challenges when integrating a hard IP cell.

Rahul Deshmukh, Open-Silicon Research Pvt Ltd -- EDN, September 8, 2010

Selection and qualification

Apart from the functionality and the functional verification environment of the hard IP cell, the following factors need to be checked while selecting the cell. These factors are related to the IP cell’s physical design integration and testability:

1. The hard IP cell needs to be available for the exact process node selected for the design. Also, the metal stack used in the hard IP cell needs to be the same as the one selected for the entire design.
2. Attention should be paid to the physical dimensions of the hard IP cell to ensure successful integration of the cell with the rest of the chip. The area impact of the hard IP cell integration needs to be checked, taking into consideration the cell’s isolation and special routing requirements, if any.
3. All of the IP models and views the various EDA tools used in the design process need to be available from the IP vendor.
4. The hard IP cell needs to support the package type selected for the design, including all of the package’s requirements, such as bump/pad pitch.
5. The IP integrator needs to check the power scheme of the hard IP. This scheme needs to work with the chip’s design-level power-distribution structure. If the hard IP cell has multiple power domains, then the IP integrator needs to ensure that the power up/down sequence synchronizes with similar requirements of other IP cells used in the design. Any special functional mode requirements, such as a power-down mode, need to be analyzed in detail and in the context of the full chip.
6. The testability of a hard IP cell is an important aspect of the chip’s development, along with ease of testing. This means that all the DFT features and their related requirements, such as additional chip-level pin requirements (to bring out some of the internal signal outputs through specific I/O buffer cells; for example, the output clock for a PLL), need to be understood and analyzed at the chip level.

Apart from the selection criteria previously discussed, the hard IP cell needs to be qualified for the target process node. This must be done to ensure its successful integration as well as error-free operation of each of the hard IP cells in the design. Some of the important qualification criteria include the following:

1. Ensure the completeness of the models/views provided for the EDA tools. Report any missing data or syntactical errors to the vendor. All of the views need to be checked for consistency. For example, pin dimensions and locations in the LEF and GDS2 views need to be consistent. However, in many cases a designer needs to come up with a plan to work around any missing or inaccurate data.
2. All of the latest versions of the IP cell’s datasheets, integration guideline documents, release notes, and errata documents must be available to the IP integrator. It is of utmost importance for the hard IP cell integrator to understand each and every requirement and guideline discussed in these documents.
3. Check the DRC and LVS results on the hard IP cell. Report any errors/warnings of these runs to the vendor and get waivers if needed.
4. Check the DRC/LVS rule-deck modifications required for the hard IP cell verification. An example of such a modification is that resistor checks that may be optional for some of the hard IP cells, but these checks may be mandatory for the complete design. Such modifications for all the hard IP cells should be collated in a single rule-deck that can be used for all of the design-level verification runs. Any conflict arising out of such modifications should be discussed and worked out with the IP vendors.

Floorplanning and physical design

1. The inductance and shielding requirements on the package for the hard IP interfaces also add restrictions on the placement of some of the hard IP cells, such as SERDES blocks. The chip designer needs to find ways to meet these restrictions. For example, an on-chip dc-to-dc converter may need double or triple bonding for a wire bond package to meet the inductance requirement on some of its power connections.
2. Similarly, the bump plan of the chip may also be affected by the IP placement location. For example, an eFuse placement may affect the bumps in the adjoining areas.
3. Interface hard IP cells such as SERDES and AFE (analog front end) play an important role in the creation of the pad ring. Integration requirements on the power domains should be checked and the required connections or breaks on the power rails must be provided after careful ESD considerations of the pad ring. If the proper ESD structures are not present in the hard IP cell, then these structures need to be added in the pad ring. Figure 1 shows an example of ESD diode structures added in the pad ring around a SERDES block.
   
   
   
   
4. Most important, the mixed-signal hard IP cells such as SERDES, AFE, DAC, and ADC have some isolation space (dead space) requirements in which no cells can be placed. The floorplan must provide for such isolation space requirements around the hard IP cells.
5. While placing a hard IP cell, any guard-ring requirements need to be analyzed. The space required for single/double/triple guard rings must be allocated around the hard IP cell. Figure 2 shows a triple guard ring example.
6. If multiple hard IP cells or multiple instantiations of the same hard IP cell share a common signal, such as a clock, then the distances between the various hard IP cells also have to be restricted to meet common signal characteristic requirements for these cells. Such common signals need to be custom routed to guarantee that the slew and delay are within the limits required by the hard IP cell.
7. Some of the hard IP cells may impose orientation restrictions that must be followed while placing these cells.
8. PLL, DAC, and ADC types of mixed-signal hard IP cells may need their analog and digital power supplies to be isolated from the rest of the core power supply.
9. Some of the hard IP cells to be placed inside the core, such as 1T SRAM memory, may also require a special power supply, which has to be isolated from the core power supply.
10. As discussed previously, certain power supply connections may come with maximum inductance and resistance requirements on the power nets. Such requirements need to be met both in the die and in the package.
11. In most cases, the power supply connections to the hard IP cells are required to be drawn through the properly selected I/O buffers on the die.
12. Some of the hard IP cells, such as OTP ROM, may require specific power connections on the IP, which need to be done to adequately ensure that current requirements are met.

Hard IP cell integration may affect some of the chip-level physical design steps, including placement, clock-tree synthesis, and routing. The following list outlines some of the important points to consider during physical design:

1. Sometimes only the phantom views of the hard IP cells (instead of the GDS2 files) are available. In such cases, additional care needs to be taken to ensure that the hard IP cell integration does not generate any DRC violations.
2. IP vendors usually ensure that metal density requirements are met within the hard IP area. However, metal fill and OD fill may need to be done over some part of the hard IP to ensure that density requirements are met.
3. The metal fill within the hard IP cell may not be sufficient for the overall chip-level VCMP (virtual chemical mechanical polishing) requirements. In such cases, the IP integrator needs to work with the IP vendor to meet or waive such requirements.
4. Decoupling the noise is an important aspect of successful hard IP integration. Some hard IP cells such as an RF block or a DAC may require additional substrate noise separation, which has to be provided by building PDIFF, NWELL, or deep NWELL guard rings around the block. The structure of these rings, including ring widths, type of ring, and number of rings, is usually decided in consultation with the IP vendor. Figure 2 shows an example of triple guard ring placed around a custom design block.
5. Most of the complex hard IP blocks do not allow routing over themselves to avoid noise through the coupled capacitance. Therefore, complete routing blockage in almost all metal layers has to be placed on such hard IP cells.
6. Some of the hard IP cells, such as AFE, DAC, and ADC, may have specific resistance requirements on their I/O connections. In other cases, the differential signals on these hard IP interfaces need to be balanced. These connections may need to be custom routed and shielded (Figure 3).
7. All such custom connections should be extracted and analyzed in SPICE to ensure that any required parameters are achieved. Some of the peripheral hard IP cells may require that die-package-board signal integrity analysis also be done to ensure that the signals connecting to such hard IP are free from any coupled noise from the IP cells.
8. Most important, the IP integrator needs to ensure that the appropriate versions of all the views of all the hard IP cells are being used in the design.

Usually at the start of the project, a test plan is built listing the details of the tests to be carried out on each of the hard IP cells. This requires crisp, clear, and accurate documentation and support from the IP vendor. Apart from this, the following parameters determine the testability of the IP cells:

1. Test models and test patterns provided by the IP vendor must be accurate enough to be able to test the hard IP cells in the integrated chip environment. Appropriate simulation models need to be made available to the IP integrator.
2. Usually scan chains are inserted in the digital portion of mixed-signal hard IP cells. While integrating cells, these scan chains need to be hooked up to either the primary ports or the other scan chains in the design. In the latter case, the scan chains may be connected to either the first or the last sections of the existing scan chains.
3. In the case of interface hard IP cells, many times the JTAG cells are implemented inside the hard IP cell itself. With this scheme, the TAP interface is provided on the core side. These TAP connections need to be connected to a TAP inserted on the chip for all of its I/O buffers.
4. Sometimes a SERDES type of complex hard IP cell requires a special wrapper to be built around it to drive and/or test some of its functionality. In such cases, the complexity of the wrapper design varies from IP cell to IP cell. Some of the hard IP cells require that all the functionality, such as complete loop-back tests, be implemented in the wrapper. In other cases, some of the hard IP cells may need the wrapper only to configure and trigger the functional tests.
5. Many hard IP cells require special connections for IDDQ tests. Such connections and the configurations required for specific tests need to be implemented and also simulated.

Apart from these parameters, the issues in pattern simulations with and without timing information (usually in the form of .sdf files) need to be resolved with the IP vendor. This is done to ensure that the patterns can be run smoothly on the ATE to test the desired faults as well as the design’s functionality.

STA (static-timing analysis)

For running STA, the hard IP cell’s interface timing needs to be modeled properly by the IP vendor in a format understood by the timing engine. The IP integrator can ensure the following:

1. Initially the timing models need to be checked for their completeness in modeling the slew, rise, and fall timing for any setup and hold time requirements.
2. In the chip-level STA, all the hard IP interface timing paths need to be specifically reported to identify critical paths. Sometimes the critical paths need to be analyzed in SPICE to make sure the timing on these signals is correct.
3. The timing reports may sometimes influence the surrounding macro placement of the IP; for example, a processor hard IP core may need the memories it accesses to be placed closer to it.
4. Special scripting in the timing environment may be needed to check some of the complex IP timing properly. For example, in a design containing a de-skew PLL, the clock insertion delay cancellation effect needs to be modeled separately by using special timing engine scripts. What makes this different is the fact that these scripts need to consider the OCV effects on the forward and feedback paths in an appropriate manner.

PDV (physical-design verification)

As previously stated, each hard IP cell must be verified against the target process rules in a standalone mode. The following are some of the example conditions in the PDV of a hard IP cell:

1. In some hard IP cells, special layers such as DNW are used. Also, some of the hard IP cells use special devices such as poly resistors, varactor diodes, MIM capacitors, and inductors. The use of such layers or devices usually calls for modifying the standard rules deck.
2. Sometimes special layers need to be added for recognizing special devices with modified logic operations. Other times the design may call for enabling some special options of the PDV tool to filter some of the devices as desired by the IP vendor. The IP integration document shall discuss all such requirements.
3. If there are multiple hard IP cells with internal devices having the same name, then such conflicts need to be resolved with the help of the respective IP vendors.
4. The case of multiple power hookups for various power domains used in the hard IP cells needs to be understood clearly. The LVS texts need to be attached on the power pins for proper LVS checks.
5. The property errors or any specific errors observed on the hard IP cells need to be reported to the IP vendor to have them corrected or waived.
6. In case of the guard rings being placed around a hard IP cell such as DAC, RF circuits, or the AFE, the guard ring connections need to be made with the proper polarities.
7. The ESD connections need to be manually reviewed to ensure that only the required power rails are continuous across the power domains and that the other rails are either disconnected or properly terminated.

Review and knowledge building

For the IP integrator, one of the key requirements of successful IP implementation is to work closely with the IP vendor and the target foundry. IP integrators need to review the hard IP cell integration with the IP vendor. All of the parameter requirements along with actual results need to be analyzed with the IP vendor. It is usually helpful to create a checklist of all of the IP parameters and requirements obtained from the integration guidelines and discussions with the IP vendors. All of these checks can then be run on the final design database to ensure compliance with all of the hard IP requirements.

Hard IP integration success lies in following rigorous checks on the integrated hard IP cells to make sure that even in the integrated environment and under specific conditions in which the hard IP cell is placed it will work correctly.

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