Fully depleted SOI shows its stuff in CPU design
An ARM Cortex M0 paper design suggest that FDSOI could be a strong contender at 20 nm.
By Ron Wilson, Editorial director -- EDN, February 10, 2011
The Silicon-on-Insulator (SOI) Industry Consortium this morning revealed results of an analysis showing a strong advantage for fully depleted SOI (FDSOI) over bulk silicon at 20 nm.Researchers at ARM Ltd designed a Cortex M0 CPU core using FDSOI cells characterized by IBM at its Albany, NY, fab. The ARM team then analyzed the design for performance at various operating voltages. They found that at 0.9V, FDSOI offered about the same performance at 20 nm as a good bulk planar LPCMOS process. But at lower operating voltages, FDSOI showed significantly higher performance gains than bulk when compared to a previous-generation bulk process.
By 0.7V-still a viable operating voltage-the ARM team estimated designers would gain 25% in performance by moving from the previous node to 20-nm LPCMOS, but 80% by moving to 20-nm FDSOI. The comparison was based on the 30K gates of logic in the M0 core, placed and routed using standard tools.
Consortium executive director Horatio Mendez said that FDSOI SRAM cells were stable at these low voltages, as well. "Our analysis of the memory cell indicates it is stable at voltages 150 mV below the minimum stable voltage for 20-nm bulk CMOS," he claimed. This could be a very significant point in the aggressive power-management strategies used in mobile devices.
The immediate importance of the findings will be for developers of mobile devices, Mendez asserted. By giving designers access to operating voltages in the range of 0.7V at high performance, FDSOI could enable a substantial jump in both capability and battery life. Mendez explained that FDSOI FETs display a steeper sub-threshold characteristic than bulk silicon FETs: in effect, they switch faster. This difference becomes more pronounced as you compare the transistors at lower supply voltages. "In many cases," Mendez said, "you can lay out fewer fingers in the FDSOI cell and still meet your delay requirements." This compactness in turn brings further savings in metal resistance and parasitic capacitance, all contributed to speed improvements and/or power savings.
The results are promising, but Mendez pointed out that they are first steps in a long journey. The FDSOI library ARM used was characterized with real wafer measurements at IBM. But ARM hasn't tried to fabricate the M0 design. There are still not market-ready libraries or RAM compilers for FDSOI, although work is reportedly under way. Nor is there a high-volume supply yet for the special FDSOI wafers, which must have an incredibly thin top silicon layer. Soitec is expected to make an announcement soon in this regard.
There is process work to do, as well. Current FDSOI FETs are simple transistors without strain engineering, and hence limited to relatively low speeds-in the low GHz region. Much opportunity remains for device engineering. And the process will generate new, probably simpler, design rules.
This simplicity could be the technology's greatest strength. Because the gate in a FD transistor completely controls the entire channel region down to the insulating box layer, the channel does not require an implant in order to achieve acceptable performance. Without the implant, the fabrication process is significantly simpler-perhaps enough simpler to compensate for the added cost of the wafers with this one point-and the entire problem of Random Dopant Fluctuation, with its huge impact on the variability of transistor threshold voltage, all but vanishes. Also, because the active channel extends all the way down to the box, there is virtually no charge trapping in the region under the channel, and hence the notorious SOI memory effect does not exist. This means that designers can work with normal CMOS timing files and timing tools without special provisions for the SOI process. Design teams can simply drop the FDSOI models into their existing flow.
The ARM announcement adds a significant new data point to the debate over the future of process technology at 20 nm and beyond. With FDSOI showing the potential for superior performance, simpler and more robust design, and no need for problematic structures such as finFETs, the weight of the argument for an FDSOI future appears to be growing.
Talkback
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Sang Kim: You are making a factor of 10 error in the Si thickness requirements. Channel thickness needs to be less than about 10nm and not 10A. In principle, at a given gate length planar FDSOI needs a channel thinner than FinFET by a factor of 2. That means, FDSOI with a 6nm channel thickness is roughly equivalent to a FinFET with channel thickness of 12nm in terms of electrostatics. While at first sight channel thickness is more relaxed in FinFET, it is much easier to produce a uniform planar structure (where thickness can be monitored by standard ellipsometry and AFM) than a 3D structure (where sophisticated spectroscopy methods are needed, and AFM simply does not work at tight fin pitch).
As for the extra scattering at the Si/BOX interface, this interface is much more well-behaved than the interface to the high-k (it's thermal oxide) and has been already shown by multiple groups not to be a limit to mobility. You are right about lack of embedded stressor in FDSOI, but eSiGe is not the only way of introducing strain, and will run out of steam sooner or later (in 14nm GR, there is less than 20nm left for eSiGe). Other strain options, that are in fact independent of device pitch, have been demonstrated on FDSOI.
The main two problems with bulk FinFET, is the leakage path at the bottom of the fin and need to high channel doping to achieve high Vt devices. So, while high performance logic might survive, SoC applications have a tough time with FinFET (Intel already delayed its 22nm logic production and their SOC seems to be even worse).
A.K. - 2011-16-11 17:20:50 PST -
Mr. Mendez highlights some of the advantages of 20nm FDSOI with zero channel doping such as low Vt variability, steeper sub-threshold slope(low Vt and leakage), and simpler process(low process cost). Some of the disadvantages are presented below. 1) For the un-doped channel the dominant leakage mechanism is DIBL(drain voltage induced barrier lowering) at the source. When drain voltage (Vd) equal to 1V is applied, the entire 1V drops across the source junction that lowers the built-in barrier, resulting in high injection leakage current. When Vd= 0.7Vis applied, 0.7V drops across the source junction, resulting in relatively smaller injection leakage current. For the un-doped channel the DIBL leakage current can not be totally eliminated unless the channel is heavily doped. However, it can be reduced by either lowering Vd or reducing the un-doped Si thickness that reduces the source injection area, but with very high price to pay. Lowering Vd means lowering transistor performance while reducing the un-doped Si thickness less than 10A (angstrom) required for 20nm may be the wafer process limit for Soitec because such extremely thin, less than 10A is thinner than the native oxide layer that grows under the normal wafer fabrication environment. For 14nm the Si layer less than 6A may be required. Furthermore, the thin oxide quality grown on BOX is inferior to that grown on the silicon substrate as seen in poor TFT (thin film transistor) electrical performance. The key question is; Soitec may not be able to produce such a thin, less than 10A of high production quality Si layer uniformly across 12 inch or larger size of wafer. 2), the stress induced mobility booster techniques widely practiced in the bulk technology can not be used because the channel is so thin and S/D junction depth so shallow that the mobility booster techniques are not effective, resulting in significant device performance degradation compared to 20nm bulk. The mobility degradation also occurs due to charge carrier scattering at the HfO2/Si interface at the top and BOX/Si interface at the bottom. Further degradation in device performance can also occur due to Vt increase as a result of quantum confinement of charge carriers. 3) Self-heating; compare Bulk device picture with FDSOI. FDSOI channel is completely surrounded by HfO2 at the top, BOX at the bottom and SiO2 at both side isolations. Therefore, FDSOI device has poor power dissipation, thus runs significantly hotter than Intel’s Bulk device due to self-heating. As a result, device degradation such as transconductance and mobility, and higher channel and S/D resistance, and higher leakage current can occur. Mr. Mendez did not compare his 20nm FDSOI device data with Intel’s 22nm for electrical performance, power and leakage current. In my personal opinion, scalability of the undoped FDSOI technology will end most likely at 20nm. Intel has been the industry first in high volume manufacturing of 45nm, 32nm, and 22nm. With its lead at 22nm Intel’s CEO Paul Otellini recently said “Intel finished its 22nm technology development and is ready for high volume manufacturing this year, and will be the main weapon to fight the process war with ARM based processors.” The war for next generation mobile/wireless process development has begun!
Sang U. Kim - 2011-16-2 10:16:10 PST -
That FDSOI has superior characteristics has been heralded since the late '90s. At that time, (1) higher SOI wafer cost, (2) Processing issues (defects, and wafer plasma charging), (3) lack of EDA tools were mentioned.
The time for FDSOI has arrived.
Alberto O. Adan - 2011-13-2 14:09:29 PST
