Complete IC simulation requires a full toolbox of hardware and software
Combining faster solvers with test benches that link analog to digital to system-level models prevents design errors.
Mike Demler, Technical Editor -- EDN, March 17, 2011
At A Glance
|
Discovering a design error after you send your
average chip to manufacturing can be costly
and embarrassing, not to mention hazardous to
your career. However, as Intel recently discovered,
finding a design error late in a complex
and widely anticipated processor SOC (system
on chip) is costly. In Intel’s case with its Sandy
Bridge chip, the design error cost as much as $1
billion (Reference 1). To avoid missing design errors, you and
your team must as thoroughly as possible simulate your design
under the conditions that the chip will see in your customer’s
application. How do you simulate a complex SOC, containing
perhaps 1 billion transistors, full of a combination of large digital
blocks, high-performance RF and analog/mixed-signal functions,
complex power management, embedded software, and gigabit
I/Os? And what do you do about reliability and aging effects? Will
your chip degrade over time, and how do you ensure that it will
be immune to environmental problems, such as static discharge?
As the simulation challenges grow, the approaches to them also become more complex. It now takes a diverse set of simulators—for analog, digital, transistor to system level, hardware/software co-verification, chip-package interface, and more. Simulation alone is not enough, however. You also need debuggers and self-checking test benches to handle the sheer volume of data that simulation will generate. Your toolbox just got heavier.
Fortunately, although 100% assurance is usually impossible, an assortment of new tools on the market can help you gain a higher degree of confidence. These tools run the gamut from fast circuit simulation to real-world emulation of system applications with embedded software and data I/O. A one-size-fits-all approach is not available, but there is a lot to choose from.
Speeding simulation
There is not much in the way of new analog simulators, according to KT Moore, vice president of simulation technology for Magma Design Automation’s custom-design business unit. Gary Smith, the founder and chief analyst at Gary Smith EDA, agrees. “There was some hope that parallel computing would be a big thing,” he says, “but it hits the Amdahl’s Law barrier of about four processors,” referring to the idea that Gene Amdahl stated in 1967 that, even when the fraction of serial work in a given problem is small—say, s—the maximum speedup you can obtain from even an infinite number of parallel processors is only 1/s.
Moore also points to parallel processing, saying that Magma has overcome the single-matrix limitation of Spice, which peaks at about 25 thousand devices, by developing methods to scale the problem across a network with the company’s FineSim simulator. This approach differs from that of FastSpice simulators, which typically break the matrix of large circuits into smaller partitions with simplified device models, potentially introducing errors and loss of accuracy. Magma’s approach is different, he explains, because the company has figured out how to maintain full BSIM (Berkeley Short Channel IGFET Model) accuracy—equivalent to conventional Spice simulators—with circuits having as many as 1 million components. FineSim can handle fully extracted postlayout simulations by distributing analysis of a single matrix across eight to 16 CPUs in two to four machines, according to Magma. This approach has changed the game, Moore adds.
Magma’s customers are looking for a more digital-centric verification method, says Moore. The ability to simulate a large design is not enough on its own because users can’t afford to look at all the waveforms. “You want to look at signals only when there is a problem and just have a pass/fail indicator otherwise.” It is possible to have conditional checking, but debugging must be more stringent. Otherwise, engineers will be unsure about whether they have missed something. “We need to think about what problem customers are trying to solve, as well as performance and accuracy,” he explains.
Simon Young, product-marketing manager at Berkeley Design Automation, also finds that capacity limitations have forced customers to use FastSpice but offers a different opinion on what is new in analog simulation. You must account for new device behaviors, such as noise, in 28-nm processes, he says. Berkeley Design has addressed this problem with the transient-noise-analysis feature in its AFS (Analog FastSpice) platform. The company claims that AFS, which has capacities as high as 10 million elements, is 10 times faster on a single-core CPU than competing versions of Spice. Semiconductor foundry TSMC (Taiwan Semiconductor Manufacturing Co) has certified AFS for its 28-nm, low-power-process design flow, and Berkeley Design is also working with GlobalFoundries, according to Young.
Engineers have been trying for many years to solve the problem of how to accurately simulate ESD (electrostatic- discharge)-protection devices. The PathFinder tool from Apache Design Solutions addresses this challenge. According to Andrew Yang, PhD, chief executive officer at the company, traditional transient solvers cannot handle the “snap-back effect” in ESD structures. In snap-back, when the voltage exceeds the trigger voltage, the IV (current-to-voltage) characteristic of the device snaps back, allowing the same or a higher amount of current to flow but at a significantly lower voltage. Negative resistance, Yang explains, causes convergence problems for traditional Spice simulators. PathFinder relies on the proprietary eSim nonlinear transient simulator, which works with standard Spice-device models. PathFinder has built-in extraction for power- and ground-bus-RLC (resistor/inductor/capacitor) elements and substrate-package parasitics. According to Yang, eight large semiconductor companies have adopted PathFinder, which can perform layout-based analysis of circuits with more than 1 million elements for ESD events, such as human-body model, machine model, and charged-device model. TSMC’s Reference Flow 11.0 also includes PathFinder.
Test-bench standards
According to Steve Bailey, director of marketing for verification and test at Mentor Graphics, as the market for simulation has matured, focus has shifted to simulation tools that can help engineers to more quickly complete verification. Although techniques such as parallel processing, multicore solvers, and multithreading improve simulator performance, they aren’t silver bullets because they don’t ease the task of finding an optimal match of solvers with partitions of a design.
In a recent survey of users, Mentor Graphics found a higher-than-expected adoption of the SV (System Verilog) HVL (hardware-verification language), with three-fourths of survey participants saying that they either were using or planned to use SV for creating test benches. One of the issues limiting SV’s adoption had been a lack of compatibility among EDA vendors’ tools. In choosing from a variety of available SV-based verification methods, you must ensure that your simulator is compatible with your test-bench libraries.
Current industry efforts to standardize a base library of functions for digital verification are addressing the portability issue. According to Bailey, the development of the new Accellera UVM (Universal Verification Methodology) Version 1.0 EA (early-adopter) standard represents a maturation of SV techniques that companies first introduced in predecessor products, starting with Mentor’s AVM (advanced verification methodology), which OVM (open verification methodology), a collaboration between Mentor and Cadence, followed. Elements of the Synopsys-developed VMM (Verification Methodology Manual) are also part of the new standard.
Michael Sanie, director of verification marketing at Synopsys, points out that Synopsys has participated in Accellera’s efforts for development of UVM, with representation by VMM expert and Synopsys Fellow Janick Bergeron. UVM incorporates VMM features, including the RAL (register-abstraction-layer) application package for memories and memory-mapped registers. Synopsys will provide native support for UVM 1.0 EA in May. Sanie also notes that users of Synopsys’ VCS HDL simulator can use OVM, so they need not wait for UVM to gain test-bench portability. He believes that the method of writing base classes for verification libraries is not the key differentiator among vendors’ tools. Vendors will continue to compete to establish an advantage in performance of the simulation engines and in debugging tools.
Automate test generation
Verification engineers can specify how the properties of a design will undergo testing with SVA (System Verilog-assertion) statements, define constraints for random stimuli, and determine how to check coverage. The ActiveProp tool from Jasper Design Automation automatically synthesizes these properties from RTL (register-transfer-level) representations of your design, or you can reuse simulation and test-bench waveforms in VCD (value-change-dump) or FSDB (fast-signal-database) formats.
According to Holly Stump, vice president
of marketing at Jasper, ActiveProp
can jump-start your ASV (assertion-based
verification) by automatically
generating assertions for formal analysis,
simulation, or emulation. ActiveProp
can work as a stand-alone tool (Figure
1), or you can link it at runtime to simulators
through an API (application-programming
interface). By performing
multiple simulation runs, you can use
the results to further refine the intelligence
of generated properties. The first
release of ActiveProp supports Synopsys
simulators.When you submit your design to ActiveProp, it analyzes and extracts critical expressions from your RTL to guide, simplify, and merge the generated properties. To initiate property synthesis from RTL, you scope your signals by identifying RTL-block signals and points of interest. You can use this information in combination with simulation data as input to ActiveProp, which then generates ranked and merged properties to reduce the number of candidates for review. Output is in the form of SV constraints, assertions, and coverages, along with reports in human-readable format.
Adoption of techniques such as constrained random stimuli in the UVM standard can help to improve verification coverage over manual, or directed, test-pattern generation, but it is also critical to eliminate redundancy in the generated test patterns. To address this problem, Mentor offers the inFact intelligent test-bench-automation tool that you can use to build test-bench components. So-called rule graphs control the activity of these components. With in- Fact, you can define rules from the specifications of the device you are verifying, such as for an industry-standard bus interface, or by applying constraints from your verification plan. When you run the simulation, the rule graphs interact with the tools and apply intelligent algorithms to more efficiently achieve the required functional coverage. The inFact tool can distribute simulation to multiple CPUs and performs load balancing. According to Mentor’s Bailey, inFact’s graph-based-testing customers have experienced as much as a 100-times speedup in the time it takes to achieve coverage, and the coverage percentage has also increased.
Integrate test benches
According to Tom Anderson, marketing manager for verification products at Cadence Design Systems, engine-level performance alone is simply not enough to solve the verification problem. The complexity of design has caused fragmentation of the verification process into niches, such as low power, RTL simulation, mixed signal, and formal analysis. Adam Sherer, Cadence’s verification-product-management director, echoes that opinion, saying that, although simulation performance is key, it isn’t enough. “As elaboration times grow for large SOCs, both faster elaboration and incremental elaboration are also necessary,” he says. “Customers need faster waveform and coverage database access and smaller database size.” With Cadence’s latest 10.2 release of the Incisive verification tools, you can link design and power intent into one verification plan and combine formal models with digital- and mixed-signal abstractions in the MDV (metric-driven-verification) cockpit. With MDV, verification engineers can merge coverage data from formal analysis with results from simulation engines into a unified SOC-level verification plan. By linking formal and dynamic analysis in MDV, you can use the formal tools to flag points in your design that are unreachable, indicating that you shouldn’t try to simulate them. Incisive can also automatically generate assertions and coverage points for simulation or formal analysis so that it is easier to define which simulators to use to execute each part of the verification plan.
Real-number models support the interface of digital- to mixed-signal behavior in Incisive. In Incisive 10.2, Cadence has optimized simulator performance for Accellera’s new UVM standard for test-bench development. Incisive integrates UVM components as native objects in simulation, with the ability to monitor transactions in the waveform viewer. Cadence has extended OVM and UVM for the ‘e’ verification language and has facilitated the use of multiple languages in test benches. It supports all IEEE-standard languages, including Verilog, VHDL (Very High Speed Integrated Circuit Hardware Description Language), PSL (property-specification language), ‘e,’ System-C, and System Verilog. To improve performance for large numbers of regression tests, Incisive’s advanced Specman option provides reseeding and dynamic loading of ‘e’-based tests, multicore ‘e’-code compilation, and the ability to shorten debugging time by mixing interpreted and compiled code.
Users of the Incisive Enterprise Simulator
also receive the Incisive verification
kit, a 1.5 million-gate design for
a prototype Ethernet-controller SOC
that acts as a demonstration vehicle
for the functional-verification concepts
(Figure 2). With the verification
kit, you can learn the new technologies
and methods through a set of self-paced
workshops. The UVM reference
flow is available as open source in the
contribution area on the UVM World
Web site.Speeding simulation
Lauro Rizzatti, general manager of Eve USA, points to EDAC (Electronic Design Automation Consortium) data that shows that emulation and HDL (hardware-description-language) accelerators are making a comeback. According to Rizzatti, software simulation can’t keep up with embedded-software development and whole-SOC verification. Although revenue in the EDA-simulation segment peaked at $532 million in 2007 and declined on an annual basis to $323 million last year, emulation has been relatively steady in the $140 million to $160 million range, accounting for a larger percentage of the overall verification market. Hardware acceleration was big 10 years ago with CPU or GPU (graphics-processing-unit) companies, says Rizzatti, but usage is now growing in the wireless, multimedia, networking, and image-processing markets. Hardware accelerators work with test benches for industry-standard Verilog-, SV-, and VHDL-based software simulators, letting you run simulation at millions of cycles per second.
The cost of acceleration hardware
has historically limited adoption, an issue
that Eve has addressed by building
its systems with Xilinx Virtex-6 FPGAs
versus ASICs. The trade-off is that the
FPGA approach has more limited visibility
of results, but Eve has now extended
debugging capability by adding
CSA (combinational signal access) to
its ZeBu (zero-bug) platform. CSA allows
you to use dynamic probing to see
the values of any RTL net in a cone of
logic between registers or memory in
your design (Figure 3). You can view
results in standard VCD or FSDB formats.
You can also do offline analysis
with CSA by generating waveforms after
your emulation run on a PC or Linux
workstation.Mentor Graphics’ Bailey has also seen an increase in the emulation- and simulation-acceleration market. Hardware acceleration is necessary for designs such as multimedia processors that require test sequences that are too long to run using software simulation alone. Mentor’s Veloce system can handle large SOC-simulation-acceleration tasks and enables software/hardware co-verification. You can use Veloce as an in-circuit emulator, connecting the model of your SOC to a physical-target design-verification environment to run embedded software and use real-world data to exercise the DUT (device under test).
Removing the barriers
The boolean nature of digital circuitry lends itself to a level of automation and abstraction that does not exist in the analog world. AMS (analog/mixed-signal) modeling languages, such as Verilog-AMS, are now more than 10 years old, but Spice and FastSpice remain the workhorses for simulation and analysis of analog behavior. Cosimulation, linking Spice or FastSpice tools with an HDL simulator, can be an effective way to bridge the gap when you need to verify mixed-signal behavior that involves analysis of analog-to-digital interactions.
All SOCs incorporate some form of analog behavior that you must simulate and verify, whether in power-management and clocking circuits or in more advanced signal-processing blocks and ADCs. With SV gaining popularity for SOC test benches, the need to cover both analog and digital behavior has led to a number of efforts to extend the SV language for AMS verification.
Synopsys’ AMS test-bench technology
extends VMM and UVM with
new constructs for analog blocks (Figure
4). The company added proprietary
SV functions to its VCS HDL
simulator to allow SV test benches
to check designs that you cosimulate
with Synopsys CustomSim. According
to Bradley Geden, CustomSim product-marketing manager at Synopsys,
the AMS test-bench integration supports
cosimulation of the VCS HDL
simulator with the XA and NanoSim
FastSpice engines within CustomSim.With the AMS test-bench technology, you can use VCS to read or write voltages or current to or from the analog simulator and convert the values to real numbers. This approach trades off performance versus accuracy compared with a discrete, piecewise-constant real-number model because co-simulation of the actual circuit derives the analog values in the AMS test bench at runtime. With the AMS test bench, you can monitor asynchronous interactions that better adapt to the unclocked nature of most analog behavior.
Components of the VCS-AMS test bench include a base class of waveform generators and checkers. Stimuli are fully customizable, and the tool provides sine-, sawtooth-, and square-wave generators. Prebuilt checkers measure common analog behaviors, such as thresholds and stability, frequency, and slew-rate measurements. With the VCS-AMS test bench, you can apply SV-constrained random-stimulus techniques to analog signals, and you can model mixed-signal transactions as an SV class. You can also apply SV monitors to analog signals to check with SVAs. By using VMM as the top-level test bench, your verification can include more complex test sequences that you can exercise without separate simulations.
To perform asynchronous sampling of analog signals, you can apply Synopsys’ adaptation of the Verilog-AMS cross function: always @(snps_cross()). As with Verilog-AMS, you must minimize the sampling rate of signals to avoid too severely affecting simulation performance. You can group signals together in SV-interface functions. By instantiating your DUT in an AMS test bench, VCS will automatically perform e2r (electrical-to-real) and r2e (real-to-electrical) transformations. You can access nodes anywhere in the hierarchy of your Spice or Verilog-AMS circuit, to get or force voltages or port currents.
To apply the SVA feature on analog signals, you can create both synchronous and asynchronous monitors. To create a synchronous monitor, you use a clock from the digital simulator to initiate a test. For an asynchronous monitor, Synopsys has added a system function that allows the analog simulator to initiate the test.
AMS verification
According to Scott Little, AMS verification engineer at Freescale Semiconductor and chairman of Accellera’s Verilog-AMS Assertions Subcommittee, a need exists for an AMS equivalent to UVM to bridge the gap between analog and digital verification. The subcommittee is attempting to define extensions to SV that will allow for the intermingling of continuous, real-time behaviors with the discrete-time nature of digital standards, such as UVM. “We are trying to add more rigor to the verification engineer’s toolbox,” he says. “When a digital-verification engineer bumps up against the analog boundary, there are not a lot of tools to address the problem. Standards are not so strong in the analog world; they are much better in digital.”
Designers must increasingly rely on digital control of analog circuits to meet performance requirements in SOCs. Engineers must also combine analog and digital functions to manage the complex low-power modes that enable packing more functions into a die without exceeding package and supply limitations. These two factors are driving the Accellera subcommittee’s efforts to define a language for AMS assertions. Researchers must address some theoretical roadblocks that remain for extending a number of SVA concepts to analog, but the committee will focus on a specified, certifiable subset, says Little. The group’s direction is to add SVA to Verilog-AMS so that engineers can write mixed-signal assertions in a digital block. The subcommittee hopes to incorporate these new functions on the next revision to the Verilog-AMS specification, which should emerge this year.
You can reach Technical Editor Mike Demler at 1-408-384-8336 and mike.demler@ubm.com.
|
Reference |
|
Editor's note: The original version of this article contained an error, which has been corrected in the text above and in the associated PDF file. "Virtex-8" was changed to "Virtex-6" on April 6, 2011.
Talkback
