The 3-D IC and you
All the talk seems to be about the 3-D IC, but does it amount to anything?
Ron Wilson, Editorial Director -- EDN, April 7, 2011
One of the most popular topics for conference sessions lately
has been the 3-D IC. Panels and papers cover a huge range
of topics, but they come down to three questions: What is
a 3-D IC, is it real, and what difference does it make? The
question of definition is surprisingly loaded. At a recent
panel, speakers divided the world of 3-D ICs into three categories.
The first category covers simply stacking up independently designed
dice and bonding them together, such as the stack of flash and DRAM dice
on the SOC (system-on-chip) die in your cell phone. In the stacking approach,
all the dice are pretested standard parts, often simply wire-bonded
together using their normal I/O bonding pads, sometimes with a silicon interposer
to move signals around for the best wire-bonding layout.The second category of 3-D ICs starts in the architectural-design phase of the system. Architects and IC designers partition the system according to the best technology in which to implement each block. Logic blocks might go into a 20-nm logic process; bulk memory, into a DRAM process; and I/Os and other AMS (analog/mixed-signal) blocks, into a large-geometry, higher-voltage process. The team would design one die in each process, optimizing the interfaces among the dice for performance needs and power constraints. They would then assemble the dice into a stack, using flip-chip technology, interposers, and TSVs (through-silicon vias) to interconnect the blocks. One panelist calls this approach technology partitioning.
In the third category, which you
could call true 3-D, designers place
each cell not in a plane on one die but
in the 3-D space they create by stacking
many dice together. TSVs become
just another element in the routing hierarchy.
In this mindset, a cell may land
in one corner of the third die in the
stack—not because of its process technology
but simply because that location
optimizes timing for the
nets in the area. You can
imagine the complexity
of a placement
algorithm
that must keep
track of the additional
delays and
space required for
the TSVs, the
thermal- and mechanical-stress
impacts of the cell
on its local neighborhood,
and so on.Each of these categories
has its own drawbacks and benefits.
Stacking primarily delivers greater
component density for space-constrained
boards. Technology partitioning
also offers greater density, but it further
hints at cost savings and significant
performance improvements from
the optimized interdie interfaces. True
3-D promises the most: to take over
as Moore’s Law dies out, giving you a
way to continue to increase transistor
density.
What does this mean to designers at the board level? In an ideal world, the three approaches would become viable one after the other, providing a continuum of improving density and performance. There’s a lot of work that must occur before we reach that ideal, however.
Clearly, stacking works today, if one partner—typically, a giant foundry—is tightly controlling a small supply chain. Technology partitioning is more problematic. Samsung recently demonstrated a wide-I/O DRAM die stacked on a logic die bearing TSVs, showing that this approach is not science fiction. Simon Burke, a Xilinx distinguished engineer, says that his company has internally produced an arrangement that stacks a dense FPGA-logic fabric in one technology atop a lower-density AMS die. Many issues still exist; these issues include diverse tool chains, lack of good TSV models, absence of thermal and mechanical 3-D modeling tools, and lack of standards.
As for true 3-D, neither design nor analysis tools exist to support it, and neither the TSVs nor the necessary die-thinning techniques are ready. KK Lin, Samsung’s director of foundry design enablement, hopes that his company will have wide I/Os available to designers in 2013, but true 3-D could still lag years behind that. In short, 3-D will come—but slowly and in waves.
Contact me at ron.wilson@ubm.com.
Talkback
-
True 3D, in my mind, would be the chip where silicon ceases to be a structural component of a die. Instead, the intermetal dielectric becomes the structure in which all active and passive devices are arranged in 3D space. There are no TSVs. The die is built up layer by layer with concurrent formation of interconnects.
When you mention science fiction, this may be closer to that category.
Michael Barger - 2011-20-4 06:42:21 PDT -
While TSV based approaches clearly have some applications, like image sensors and stacking a single layer of memory over logic, I firmly believe that the maximum benefits in terms of cost, power budget and performance will only realized with monolithic 3-D ICs. Our work (www.monolithic3d.com) has resulted in a number of approaches to scaling "up" that allow for extremely high inter-die interconnect density (roughly the same order of magnitude as vias between metal layers), without incurring severe penalties in either foundry costs or yields. True monolithic 3-D is a lot closer than you think.
Dean Stevens - 2011-14-4 15:13:56 PDT -
The Russians used the technology of stacking chips way back in the seventies. As they had not the resources as the West they had to find other means to save weigth, board space and material. Why it takes so long for the West to adapt the idea is a mistery to me. I still see the various chips produced by the Russians shown on tv and different magazines after the USSR collapsed.
Tognon Marco - 2011-13-4 01:06:51 PDT -
3D chip stacking has been around since the late 1970's. One picture that shows a Mostek 38P70/P73 nmos IC with EEPROM/EPROM stacked on top. Search for "38p70 pictures" and you can see a few. While at the EDP Symposium this last week, Steve Leibson mentioned he used this during his design tenure at HP.
This novel approach was very successful for customers that either had low volume production or wanted to debug their ROM code before a masked version was created. A simple process that required the ROM code to be converted into a single mask with/without depletion implant windows for each bit in the code and provided a much cheaper unit price. Thousands of different designs successfully used this microcontroller and pre-production development environment. And yes, yields could be tempermental based on variations in the mfg process but could be resolved.
Rather than using TSVs, solderable sockets were used and rather than current interposers it was a ceramic package. Assembly was performed between Penang and Carrollton sites.
Bill Martin - 2011-12-4 13:01:43 PDT -
The benefits of 3D for space constraints is obvious and will justify some effort in this area. However, 3D for transistor density should deliver superior cost to really address Moore's Law.
Shrinking feature sizes has resulted in dramatically lower cost for a given function, or dramatically more function for the same cost. I question whether 3D IC's of any type deliver dramatic cost savings, if any savings at all.
Stacked die create savings of packaging at best,which may be entirely offset by the costs of the stacking process.
True 3D will require many additional process steps on each layer, so any raw silicon wafer and packaging savings may be entirely consumed by all the extra processing, improved signal routing not withstanding.
Does the emperor have no clothes? Is everyone so entertained by this discussion that no one wants to state the obvious.
I'm sure there will be some performance benefits from 3D but it remains to be seen whether this is an esoteric niche or a truly beneficial technology direction.
Graphene, GaN and silicon wire transistors all seem more likely to me to result in the kind of cost savings and/or performance improvements we need going forward.
Bill Teasley - 2011-8-4 08:08:03 PDT
